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| hc11 MC68HC11d3 technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data iii table of contents paragraph number page number section 1 introduction 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 section 2 pin descriptions 2.1 v dd , v ss , and ev ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 reset (reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 crystal driver and external clock input (xtal, extal) . . . . . . . . . . . . . . . . . . . . 2-3 2.4 e-clock output (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.5 interrupt request (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.6 non-maskable interrupt (xirq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.7 moda and modb (moda/lir ,and modb/v stby ) . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.8 pd6/as . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.9 pd7/r/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.10 port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -6 2.10.1 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.10.2 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.10.3 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.10.4 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 section 3 central processing unit 3.1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 accumulators a, b, and d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.2 index register x (ix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.3 index register y (iy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.6.1 carry/borrow (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.6.2 overflow (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.6.3 zero (z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.6.4 negative (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.6.5 interrupt mask (i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.6.6 half carry (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.6.7 x interrupt mask (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.6.8 stop disable (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2 data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -6 3.3 opcodes and operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2.1 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2.2 indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2.3 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2.4 relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . iv technical data table of contents (cont.) paragraph number page number section 4 operating modes and on-chip memory 4.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2 expanded multiplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.3 special test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.4 bootstrap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1 priority and mode select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.2.2 system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.2.1 config register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.2.2 init register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.2.2.3 option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 section 5 resets and interrupts 5.1 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2 external reset (reset ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.3 cop reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.4 clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.5 option register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.6 config register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 4 5.2.1 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.3 parallel i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2.4 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2.5 real-time interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2.6 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2.7 cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.2.8 sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.2.9 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.2.10 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.3 reset and interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.3.1 highest priority interrupt and miscellaneous register . . . . . . . . . . . . . . . . . 5-7 5.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4.1 interrupt recognition and register stacking . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4.2 non-maskable interrupt request xirq . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4.3 illegal opcode trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4.4 software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4.5 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4.6 reset and interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.5 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5.1 wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5.2 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 section 6 parallel i/o 6.1 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.3 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data v table of contents (cont.) paragraph number page number 6.4 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.5 parallel i/o control register (pioc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 section 7 serial communications interface 7.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 1 7.2 transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3 receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.4 wake-up feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.4.1 idle-line wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.4.2 address-mark wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.5 sci error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.6 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 5 7.6.1 serial communications data register (scdr) . . . . . . . . . . . . . . . . . . . . . . 7-5 7.6.2 serial communications control register 1 (sccr1) . . . . . . . . . . . . . . . . . . 7-5 7.6.3 serial communications control register 2 (sccr2) . . . . . . . . . . . . . . . . . . 7-6 7.6.4 serial communication status register (scsr) . . . . . . . . . . . . . . . . . . . . . . 7-7 7.6.5 baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.7 status flags and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 section 8 serial peripheral interface 8.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 spi transfer formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2.1 clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3 spi signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3.1 master in slave out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.2 master out slave in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.4 slave select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4 spi system errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.5 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 5 8.5.1 serial peripheral control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5.2 serial peripheral status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.3 serial peripheral data i/o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 section 9 timing system 9.1 timer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9- 4 9.2.1 timer control 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.2.2 timer input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.2.3 timer input capture 4/output compare 5 register . . . . . . . . . . . . . . . . . . . 9-6 9.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.3.1 timer output compare registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.3.2 timer compare force register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.3 output compare mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.4 output compare 1 data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.5 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.6 timer control 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.7 timer interrupt mask 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.8 timer interrupt flag 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . vi technical data table of contents (cont.) paragraph number page number 9.3.9 timer interrupt mask 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.3.10 timer interrupt flag 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.1 timer interrupt flag 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.4.2 pulse accumulator control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.5 computer operating properly watchdog function . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.6 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.6.1 pulse accumulator control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.6.2 pulse accumulator count register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.6.3 pulse accumulator status and interrupt bits . . . . . . . . . . . . . . . . . . . . . . . 9-18 appendix a electrical characteristics appendix b mechanical data and ordering information b.1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.2 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 appendix c development support c.1 development system tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 c.2 MC68HC11d3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC11d3 ta figure title page list of illustrations 1-1 MC68HC11d3 block diagram ........................................................................ 1-2 2-1 pin assignments for 44-pin plcc ................................................................. 2-1 2-2 pin assignments for 40-pin dip ..................................................................... 2-2 2-3 external reset circuit ..................................................................................... 2-3 2-4 common crystal connections ........................................................................ 2-3 2-5 external oscillator connections ..................................................................... 2-4 2-6 one crystal driving two mcus ..................................................................... 2-4 3-1 programming model ....................................................................................... 3-1 3-2 stacking operations ....................................................................................... 3-3 4-1 address/data demultiplexing ......................................................................... 4-2 4-2 MC68HC11d3 memory map .......................................................................... 4-3 4-3 ram standby modb/v stby connections ...................................................... 4-6 5-1 processing flow out of reset (1 of 2) .......................................................... 5-12 5-2 interrupt priority resolution (1 of 2) ............................................................. 5-14 5-3 interrupt source resolution within sci ........................................................ 5-16 7-1 sci transmitter block diagram ...................................................................... 7-2 7-2 sci receiver block diagram .......................................................................... 7-3 7-3 sci baud rate diagram ............................................................................... 7-10 7-4 interrupt source resolution within sci ........................................................ 7-12 8-1 spi block diagram ......................................................................................... 8-2 8-2 spi transfer format ....................................................................................... 8-3 9-1 timer clock divider chains ............................................................................ 9-2 9-2 capture/compare block diagram .................................................................. 9-4 9-3 pulse accumulator ....................................................................................... 9-16 a-1 test methods ..................................................................................................a-3 a-2 timer inputs ...................................................................................................a-4 a-3 por and external reset timing diagram ......................................................a-5 a-4 stop recovery timing diagram ................................................................... a-6 a-5 wait recovery timing diagram ....................................................................a-7 a-6 port write timing diagram .............................................................................a-8 a-7 port read timing diagram .............................................................................a-8 a-8 multiplexed expansion bus timing diagram ................................................a-10 a-9 spi master timing (cpha = 0) ....................................................................a-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . techni (continued) figure title page list of illustrations a-10 spi master timing (cpha = 1) ....................................................................a-12 a-11 spi slave timing (cpha = 0) ......................................................................a-13 a-12 spi slave timing (cpha = 1) ......................................................................a-13 b-1 40-pin dip ......................................................................................................b-1 b-2 44-pin plcc ..................................................................................................b-2 b-3 44-pin qfp .....................................................................................................b-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC11d3 ta table title page list of tables 2-1 port signal functions............................................................................................. 2-6 3-2 instruction set........................................................................................................ 3-8 4-1 register and control bit assignments ................................................................. 4-4 4-2 hardware mode select summary.......................................................................... 4-6 4-3 ram mapping ........................................................................................................ 4-9 4-4 register mapping................................................................................................... 4-9 5-1 cop time-out........................................................................................................ 5-2 5-2 reset cause, reset vector, and operating mode ................................................ 5-4 5-3 highest priority interrupt selection ........................................................................ 5-8 5-4 interrupt and reset vector assignments ............................................................... 5-9 5-5 stacking order on entry to interrupts .................................................................. 5-10 7-1 baud rate prescale selects .................................................................................. 7-8 7-2 baud rate selects ................................................................................................ 7-9 9-1 timer summary ..................................................................................................... 9-3 9-2 timer control configuration................................................................................... 9-5 9-3 pulse accumulator timing ................................................................................... 9-16 a-1 maximum ratings..................................................................................................a-1 a-2 thermal characteristics ........................................................................................a-1 a-3 dc electrical characteristics.................................................................................a-2 a-4 control timing .......................................................................................................a-4 a-5 peripheral port timing...........................................................................................a-8 a-6 expansion bus timing...........................................................................................a-9 a-7 serial peripheral interface timing .......................................................................a-11 b-1 ordering information .............................................................................................b-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction technical data 1-1 section 1 introduction the MC68HC11d3 and MC68HC11d0 are rom-based high-performance microcon- trollers (mcus) based on the MC68HC11e9 design. members of the dx series are de- rived from the same mask and feature a high speed multiplexed bus capable of running at up to 3 mhz, and a fully static design that allows operations at frequencies to dc. the only difference between the mcus in the dx series is whether or not the rom has been tested and guaranteed. 1.1 features ? MC68HC11 cpu ? power saving stop and wait modes ? 4 kbytes of on-chip rom ? 192 bytes of on-chip ram (all saved during standby) ? 16-bit timer system 3 input capture (ic) channels 4 output compare (oc) channels one ic or oc channel (software selectable) ? 8-bit pulse accumulator ? real-time interrupt circuit ? computer operating properly (cop) watchdog system ? synchronous serial peripheral interface (spi) ? asynchronous nonreturn to zero (nrz) serial communications interface (sci) ? 26 input/output (i/o) pins 16 bidirectional i/o pins 3 input only pins 3 output only pins (one output only pin in the 40-pin package) ? available in a 44-pin plastic leaded chip carrier (plcc) and 40-pin dual in-line package (dip) 1.2 structure refer to figure 1-1 , which shows the structure of the MC68HC11d3 mcu. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction 1-2 technical data figure 1-1 MC68HC11d3 block diagram spi sci port d control extal xtal e oscillator clock logic interrupt logic moda/ lir modb/ v stby timer system cpu cop pulse accumulator strobe and handshake port b pb7/a15 pb6/a14 pb5/a13 pb4/a12 pb3/a11 pb2/a10 pb1/a9 pb0/a8 port c pc7/a7/d7 pc6/a6/d6 pc5/a5/d5 pc4/a4/d4 pc3/a3/d3 pc2/a2/d2 pc1/a1/d1 pc0/a0/d0 pd7/r/w pd6/as pd5/ss pd4/sck pd3/mosi pd2/miso pd1/txd pd0/rxd control port a pa7/pai/oc1 pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/oc5/oc1 pa2/ic1 pa1/ic2 pa0/ic3 bus expansion parallel i/o address address/data r/w as ss sck periodic interrupt mode control xirq irq / reset mosi miso 192 bytes ram 4 kbytes rom v ss v dd txd rxd control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions technical data 2-1 section 2 pin descriptions the MC68HC11d3 is available packaged as a 40-pin dual in-line package (dip), a 44- pin plastic leaded chip carrier (plcc), or a 44-pin quad flat pack (qfp). most pins on this mcu serve two or more functions, as described in the following paragraphs. refer to figure 2-1 and figure 2-2, which shows the MC68HC11d3 pin assignments. figure 2-1 pin assignments for 44-pin plcc pc4/addr4 pc5/addr5 pc6/addr6 pc7/addr7 xirq/v pp pd7/r/ w pd6/as reset irq pd0/rxd pd1/txd pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 nc pa0/ic3 pa1/ic2 pc3/addr3 pc2/addr2 pc1/addr1 pc0/addr0 v ss ev ss xtal extal e moda/ lir modb/v stby pd2/miso pd3/mosi pd4/sck pd5/ ss v dd pa7/pa i /oc1 pa6/oc 2 /oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/ic4/oc5/oc1 pa2/ic1 7 8 9 10 11 12 13 14 15 16 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 17 pb1/addr9 38 pb0/addr8 39 MC68HC(7)11d3 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc... pin descriptions 2-2 technical data figure 2-2 pin assignments for 40-pin dip 2.1 v dd , v ss , and ev ss power is supplied to the mcu through v dd and v ss . v ss is the power supply, and v ss is ground. ev ss , available on the 44-pin plcc, is an additional ground pin that must be grounded with v ss . the mcu operates from a single 5-volt (nominal) power supply. very fast signal transitions occur on the mcu pins. the short rise and fall times place high, short duration current demands on the power supply. to prevent noise problems, provide good power supply bypassing at the mcu. also, use bypass capac- itors that have good high-frequency characteristics and situate them as close to the mcu as possible. bypass requirements vary, depending on how heavily the mcu pins are loaded. 2.2 reset (reset ) an active low bidirectional control signal, reset , acts as an input to initialize the mcu to a known startup state. it also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or cop watchdog circuit. the cpu distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic one in less than two e-clock cycles after a reset has oc- curred. it is not advisable to connect an external resistor-capacitor (rc) power-up de- lay circuit to the reset pin of m68hc11 devices because the circuit charge time pc7/addr7 xirq /v pp pd7/r/w pd6/as reset irq pd0/rxd pd1/txd pd2/miso pd3/mosi 9 10 11 12 13 14 15 16 17 18 pd4/sck 19 pd5/ss 20 pc6/addr6 8 pc5/addr5 7 pc4/addr4 6 pc3/addr3 5 pc2/addr2 4 pc1/addr1 3 pc0/addr0 2 v ss 1 pb5/addr13 pb6/addr14 pb7/addr15 pa0/ic3 pa1/ic2 pa2/ic1 pa3/ic4/oc5/oc1 pa5/oc3/oc1 pa7/pai/oc1 v dd 30 29 28 27 26 25 24 23 22 21 pb4/addr12 31 pb3/addr11 32 pb2/addr10 33 pb1/addr9 34 pb0/addr8 35 modb/v stby 36 moda/lir 37 e 38 extal 39 xtal 40 MC68HC(7)11d3 d3 40-pin dip f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions technical data 2-3 constant can cause the device to misinterpret the type of reset that occurred. refer to section 5 resets and interrupts for further information. figure 2-3 illustrates a reset circuit that uses an external switch. use a low voltage interrupt circuit, however, to prevent corruption of ram. figure 2-3 external reset circuit 2.3 crystal driver and external clock input (xtal, extal) these two pins provide the interface for either a crystal or a cmos compatible clock to control the internal clock generator circuitry. the frequency applied to these pins is four times higher than the desired e-clock rate. the xtal pin is normally left unterminated when an external cmos compatible clock input is connected to the extal pin. however, a 10 k w to 100 k w load resistor con- nected from xtal to ground can be used to reduce rfi noise emission. the xtal output is normally intended to drive only a crystal. the xtal output can be buffered with a high impedance buffer, or it can be used to drive the extal input of another m68hc11. in all cases, use caution around the oscillator pins. load capacitances shown in the oscillator circuits include all stray layout capacitances. refer to figure 2-4 , figure 2- 5 , and figure 2-6 . figure 2-4 common crystal connections ext reset circuit 4.7 k w to reset v dd mc34(0/1)64 reset gnd in of m68hc11 2 1 3 v dd 10 m w * this value includes all stray capacitances. mcu 25 pf * 25 pf * extal xtal 4 x e crystal common xtal conn f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2-4 technical data figure 2-5 external oscillator connections figure 2-6 one crystal driving two mcus 2.4 e-clock output (e) e is the output connection for the internally generated e clock. the signal from e is used as a timing reference. the frequency of the e-clock output is one fourth that of the input frequency at the xtal and extal pins. when e-clock output is low, an in- ternal process is taking place. when it is high, data is being accessed. all clocks, in- cluding the e clock, are halted when the mcu is in stop mode. the e clock can be turned off in single-chip modes to reduce the effects of radio frequency interference (rfi). 2.5 interrupt request (irq ) the irq input provides a means of applying asynchronous interrupt requests to the mcu. either negative edge-sensitive triggering or level-sensitive triggering is program selectable (option register). irq is always configured to level-sensitive triggering at reset. connect an external pullup resistor, typically 4.7 k w , to v dd when irq is used in a level sensitive wired-or configuration. 2.6 non-maskable interrupt (xirq ) the xirq input provides a means of requesting a nonmaskable interrupt after reset initialization. during reset, the x bit in the condition code register (ccr) is set and any interrupt is masked until mcu software enables it. because the xirq input is level- nc mcu extal xtal 4 x e cmos-compatible ext extal conn external oscillator 10 m w * this value includes all stray capacitances. first 25 pf * 25 pf * extal xtal 4 x e crystal dual-mcu xtal conn nc second extal xtal 220 w mcu mcu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions technical data 2-5 sensitive, it can be connected to a multiple-source wired-or network with an external pullup resistor to v dd . xirq is often used as a power loss detect interrupt. whenever xirq or irq are used with multiple interrupt sources (irq must be config- ured for level-sensitive operation if there is more than one source of irq interrupt), each source must drive the interrupt input with an open-drain type of driver to avoid contention between outputs. there should be a single pullup resistor near the mcu interrupt input pin (typically 4.7 k w ). there must also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low until the mcu rec- ognizes and acknowledges the interrupt request. if one or more interrupt sources are still pending after the mcu services a request, the interrupt line will still be held low and the mcu will be interrupted again as soon as the interrupt mask bit in the mcu is cleared (normally upon return from an interrupt). refer to section 5 resets and interrupts . 2.7 moda and modb (moda/lir ,and modb/v stby ) during reset, moda and modb select one of the four operating modes. refer to sec- tion 4 operating modes and on-chip memory . after the operating mode has been selected, the lir pin provides an open-drain output to indicate that execution of an instruction has begun. a series of e-clock cycles occurs during execution of each instruction. the lir signal goes low during the first e-clock cycle of each instruction (opcode fetch). this output is provided for assistance in pro- gram debugging. the v stby pin is used to input ram standby power. when the voltage on this pin is more than one mos threshold (about 0.7 volts) above the v dd voltage, the internal 192-byte ram and part of the reset logic are powered from this signal rather than the v dd input. this allows ram contents to be retained without v dd power applied to the mcu. reset must be driven low before v dd is removed and must remain low until v dd has been restored to a valid level. 2.8 pd6/as this pin performs either of two separate functions, depending on the operating mode. in single-chip and bootstrap modes, the pin functions as input/output port d bit 6. in the expanded multiplexed and test modes, it provides an address strobe (as) function. the as can demultiplex the address and data signals at port c. refer to section 4 operating modes and on-chip memory for further information. 2.9 pd7/r/w this pin provides two separate functions, depending on the operating mode. in single- chip and bootstrap modes, pd7/r/w acts as input/output port d bit 7. refer to sec- tion 6 parallel i/o for further information. in expanded multiplexed and test modes, pd7/r/w performs a read/write function. pd7/r/w controls the direction of transfers on the external data bus. a high on this pin indicates that a read cycle is in progress. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2-6 technical data 2.10 port signals in the 44-pin plcc package, 32 input/output lines are arranged into four 8-bit ports: a, b, c, and d. the lines of ports b, c, and d are fully bidirectional. each of these four ports serves a purpose other than i/o, depending on the operating mode or peripheral functions selected. note that ports b, c, and two bits of port d are available for i/o functions only in single-chip and bootstrap modes. refer to table 2-1 for details about the 32 port signals' functions within different operating modes. *in the 40-pin package, pins pa4 and pa6 are not bonded. their associated i/o and output compare functions are not available externally. they can still be used as internal software timers, however. table 2-1 port signal functions port/bit single-chip and bootstrap mode expanded multiplexed and special test mode pa0 pa0/ic3 pa1 pa1/ic2 pa2 pa2/ic1 pa3 pa3/oc5/ic4/oc1 pa4* pa4/oc4/oc1 pa5 pa5/oc3/oc1 pa6* pa6/oc2/oc1 pa7 pa7/pai/oc1 pb0 pb0 addr8 pb1 pb1 addr9 pb2 pb2 addr10 pb3 pb3 addr11 pb4 pb4 addr12 pb5 pb5 addr13 pb6 pb6 addr14 pb7 pb7 addr15 pc0 pc0 addr0/data0 pc1 pc1 addr1/data1 pc2 pc2 addr2/data2 pc3 pc3 addr3/data3 pc4 pc4 addr4/data4 pc5 pc5 addr5/data5 pc6 pc6 addr6/data6 pc7 pc7 addr7/data7 pd0 pd0/rxd pd1 pd1/txd pd2 pd2/miso pd3 pd3/mosi pd4 pd4/sck pd5 pd5/ss pd6 pd6 as pd7 pd7 r/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions technical data 2-7 2.10.1 port a port a can be read at any time. inputs return the pin level; outputs return the pin driver input level. if written, port a stores the data in an internal latch. it drives the pins only if they are configured as outputs. writes to port a do not change the pin state when the pins are configured for timer output compares. out of reset, port a bits 7 and [3:0] are general high impedance inputs, while bits [6:4] are outputs, driving low. bidirectional lines pa7 and pa3 in pactl are not changed and do not have any effect on those bits. when the output compare functions associ- ated with these pins are disabled, the ddr bits in pactl govern the i/o state. refer to section 6 parallel i/o . 2.10.2 port b port b is an 8-bit general-purpose i/o port with a data register (portb) and a data direction register (ddrb). in single-chip mode, port b pins are general-purpose i/o pins (pb[7:0]). in the expanded multiplexed mode, all of the port b pins act as the high- order address bits (addr[15:8]) of the address bus. port b can be read at any time. inputs return the sensed levels at the pin, while outputs return the input level of the port b pin drivers. if port b is written, the data is stored in an internal latch and can be driven only if port b is configured as general-purpose out- puts in single-chip or bootstrap modes. port b pins are general-purpose inputs out of reset in single-chip and bootstrap modes. these pins are outputs (the high order address bits) out of reset in expanded multiplexed and test modes. refer to section 6 parallel i/o . 2.10.3 port c port c is an 8-bit general-purpose i/o port with a data register (portc) and a data direction register (ddrc). in the single-chip mode, port c pins are general-purpose i/ o pins (pc[7:0]). in the expanded multiplexed mode, port c pins are configured as multiplexed address/data pins. during the address cycle, bits [7:0] of the address are output on pc[7:0]. during the data cycle, bits [7:0] (pc[7:0]) are bidirectional data pins controlled by the r/w signal. port c can be read at any time. inputs return the sensed levels at the pin, while outputs return the input level of the port c pin drivers. if port c is written, the data is stored in an internal latch and can be driven only if port c is configured for general-purpose out- puts in single-chip or bootstrap mode. port c pins are general-purpose inputs out of reset in single-chip and bootstrap modes. these pins are multiplexed low-order ad- dress and data bus lines out of reset in expanded multiplexed and test modes. the cwom control bit in the pioc register disables port c's p-channel output driver. cwom simultaneously affects all eight bits of port c. because the n-channel driver is not affected by cwom, setting cwom causes port c to become an open-drain-type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2-8 technical data output port suitable for wired-or operation. in wired-or mode (a port c bit is at logic level zero), it is actively driven low by the n-channel driver. when a port c bit is at logic level one, the associated pin has high impedance, as neither the n- nor the p-channel devices are active. it is customary to have an external pullup resistor on lines that are driven by open-drain devices. port c can only be configured for wired-or operation when the mcu is in single-chip mode. refer to section 6 parallel i/o for addi- tional information about port c functions. 2.10.4 port d port d, an 8-bit, general-purpose i/o port has a data register (portd) and a data di- rection register (ddrd). the eight port d bits (d[7:0]) can be used for general-purpose i/o, for the serial communications interface (sci) and serial peripheral interface (spi) subsystems, or for bus data direction control. port d can be read at any time and inputs return the sensed levels at the pin; whereas, the outputs return the input level of the port d pin drivers. if portd is written, the data is stored in an internal latch, and can be driven only if port d is configured for general- purpose output. this port shares functions with the on-chip sci and spi subsystems, while bits 6 and 7 control the direction of data flow on the bus in expanded and special test modes. refer to section 6 parallel i/o . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit technical data 3-1 section 3 central processing unit this section presents information on m68hc11 central processing unit (cpu) archi- tecture, data types, addressing modes, the instruction set, and special operations, such as subroutine calls and interrupts. the cpu is designed to treat all peripheral, i/o, and memory locations identically as addresses in the 64 kbyte memory map. this is referred to as memory-mapped i/o. there are no special instructions for i/o that are separate from those used for memory. this architecture also allows accessing an operand from an external memory location with no execution-time penalty. 3.1 cpu registers m68hc11 cpu registers are an integral part of the cpu and are not addressed as if they were memory locations. the seven registers, discussed in the following para- graphs, are shown in figure 3-1 . figure 3-1 programming model 8-bit accumulators a & b 70 70 15 0 ab d ix iy sp pc 70 c v z n i h x s or 16-bit double accumulator d index register x index register y stack pointer program counter carry/borrow from msb overflow zero negative i-interrupt mask half carry (from bit 3) x-interrupt mask stop disable condition codes hc11 prog model f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit 3-2 technical data 3.1.1 accumulators a, b, and d accumulators a and b are general-purpose 8-bit registers that hold operands and re- sults of arithmetic calculations or data manipulations. for some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumu- lator d. although most operations can use accumulators a or b interchangeably, the following exceptions apply: the abx and aby instructions add the contents of 8-bit accumulator b to the contents of 16-bit register x or y, but there are no equivalent instructions that use a instead of b. the tap and tpa instructions transfer data from accumulator a to the condition code register, or from the condition code register to accumulator a, however there are no equivalent instructions that use b rather than a. the decimal adjust accumulator (daa) instruction is used after binary-coded decimal (bcd) arithmetic operations, but there is no equivalent bcd instruction to adjust ac- cumulator b. the add, subtract, and compare instructions associated with both a and b (aba, sba, and cba) only operate in one direction, making it important to plan ahead to ensure the correct operand is in the correct accumulator. 3.1.2 index register x (ix) the ix register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. the ix register can also be used as a counter or as a temporary storage register. 3.1.3 index register y (iy) the 16-bit iy register performs an indexed mode function similar to that of the ix reg- ister. however, most instructions using the iy register require an extra byte of machine code and an extra cycle of execution time because of the way the opcode map is im- plemented. refer to 3.3 opcodes and operands for further information. 3.1.4 stack pointer (sp) the m68hc11 cpu has an automatic program stack. this stack can be located any- where in the address space and can be any size up to the amount of memory available in the system. normally the sp is initialized by one of the first instructions in an appli- cation program. the stack is configured as a data structure that grows downward from high memory to low memory. each time a new byte is pushed onto the stack, the sp is decremented. each time a byte is pulled from the stack, the sp is incremented. at any given time, the sp holds the 16-bit address of the next free location in the stack. figure 3-2 is a summary of sp operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit technical data 3-3 figure 3-2 stacking operations sp stack ccr sp+1 accb sp+2 acca sp+3 ix h sp+4 ix l sp+5 iy h sp+6 iy l sp+7 rtn h sp+8 sp+9 70 rtn l pc main program $9d = jsr jsr, jump to subroutine dd next main instr. rtn direct pc main program $ad = jsr ff next main instr. rtn indexed, x pc main program $18 = pre ff next main instr. rtn indexed, y $ad = jsr pc main program $bd = pre ll next main instr. rtn indexed, y hh jmp, jump pc main program $6e = jmp ff next main instr. x + ff indexed, x indexed, y extended pc main program $18 = pre $6e = jmp next main instr. x + ff ff pc main program $7e = jmp hh next main instr. hh ll ll sp stack ccr sp+1 accb sp+2 acca sp+3 ix h sp+4 ix l sp+5 iy h sp+6 iy l sp+7 rtn h sp+8 sp+9 70 rtn l pc interrupt routine $3e = wai spC9 stack ccr spC8 accb spC7 acca spC6 ix h spC5 ix l spC4 iy h spC3 iy l spC2 rtn h spC1 sp 70 rtn l pc main program $3f = swi pc main program $3e = wai swi, software interrupt wai, wait for interrupt wai, wait for interrupt spC2 stack rtn h spC1 rtn l sp 70 pc main program $8d = bsr pc main program $39 = rts bsr, branch to subroutine rts, return from subroutine sp stack rtn h sp+1 rtn l sp+2 70 legend: rtn = address of next instruction in main program to be executed upon return from subroutine rtn h = most significant byte of return address rtn l = least significant byte of return address = stack pointer position after operation is complete dd = 8-bit direct address ($0000C$00ff) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $ff (256) is added to index hh = high-order byte of 16-bit extended address ll = low-order byte of 16-bit extended address rr= signed relative offset $80 (C128) to $7f (+127) (offset relative to the address following the machine code offset byte) hc11 stack operations f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit 3-4 technical data when a subroutine is called by a jump to subroutine (jsr) or branch to subroutine (bsr) instruction, the address of the instruction after the jsr or bsr is automatically pushed onto the stack, least significant byte first. when the subroutine is finished, a return from subroutine (rts) instruction is executed. the rts pulls the previously stacked return address from the stack, and loads it into the program counter. execu- tion then continues at this recovered return address. when an interrupt is recognized, the current instruction finishes normally, the return address (the current value in the program counter) is pushed onto the stack, all of the cpu registers are pushed onto the stack, and execution continues at the address specified by the vector for the interrupt. at the end of the interrupt service routine, an rti instruction is executed. the rti instruction causes the saved registers to be pulled off the stack in reverse order. program execution resumes at the return address. there are instructions that push and pull the a and b accumulators and the x and y index registers. these instructions are often used to preserve program context. for ex- ample, pushing accumulator a onto the stack when entering a subroutine that uses ac- cumulator a, and then pulling accumulator a off the stack just before leaving the subroutine, ensures that the contents of a register will be the same after returning from the subroutine as it was before starting the subroutine. 3.1.5 program counter (pc) the program counter, a 16-bit register, contains the address of the next instruction to be executed. after reset, the program counter is initialized from one of six possible vectors, depending on operating mode and the cause of reset. 3.1.6 condition code register (ccr) this 8-bit register contains five condition code indicators (c, v, z, n, and h), two inter- rupt masking bits, (irq and xirq) and a stop disable bit (s). in the m68hc11 cpu, condition codes are automatically updated by most instructions. for example, load ac- cumulator a (ldaa) and store accumulator a (staa) instructions automatically set or clear the n, z, and v condition code flags. pushes, pulls, add b to x (abx), add b to y (aby), and transfer/exchange instructions do not affect the condition codes. refer to table 3-2 , which shows what condition codes are affected by a particular instruc- tion. 3.1.6.1 carry/borrow (c) the c bit is set if the arithmetic logic unit (alu) performs a carry or borrow during an arithmetic operation. the c bit also acts as an error flag for multiply and divide opera- table 3-1 reset vector comparison por or pin clock monitor cop watchdog normal $fffe, f $fffc, d $fffa, b test or boot $bffe, f $bffc, d $bffa, b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit technical data 3-5 tions. shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. 3.1.6.2 overflow (v) the overflow bit is set if an operation causes an arithmetic overflow. otherwise, the v bit is cleared. 3.1.6.3 zero (z) the z bit is set if the result of an arithmetic, logic, or data manipulation operation is zero. otherwise, the z bit is cleared. compare instructions do an internal implied sub- traction and the condition codes, including z, reflect the results of that subtraction. a few operations (inx, dex, iny, and dey) affect the z bit and no other condition flags. for these operations, only = and - conditions can be determined. 3.1.6.4 negative (n) the n bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (msb = 1). otherwise, the n bit is cleared. a result is said to be negative if its most significant bit (msb) is a one. a quick way to test whether the contents of a mem- ory location has the msb set is to load it into an accumulator and then check the status of the n bit. 3.1.6.5 interrupt mask (i) the interrupt request (irq ) mask (i bit) is a global mask that disables all maskable in- terrupt sources. while the i bit is set, interrupts can become pending, but the operation of the cpu continues uninterrupted until the i bit is cleared. after any reset, the i bit is set by default and can only be cleared by a software instruction. when an interrupt is recognized, the i bit is set after the registers are stacked, but before the interrupt vector is fetched. after the interrupt has been serviced, a return from interrupt instruction is normally executed, restoring the registers to the values that were present before the interrupt occurred. normally, the i bit is zero after a return from interrupt is executed. although the i bit can be cleared within an interrupt service routine, nesting interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. refer to section 5 resets and interrupts . 3.1.6.6 half carry (h) the h bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an add, aba, or adc instruction. otherwise, the h bit is cleared. half carry is used during bcd operations. 3.1.6.7 x interrupt mask (x) the xirq mask (x) bit disables interrupts from the pin. after any reset, x is set by de- fault and must be cleared by a software instruction. when an interrupt is recognized, the x and i bits are set after the registers are stacked, but before the interrupt vector is fetched. after the interrupt has been serviced, an rti instruction is normally execut- ed, causing the registers to be restored to the values that were present before the in- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit 3-6 technical data terrupt occurred. the x interrupt mask bit is set only by hardware (or acknowledge). x is cleared only by program instruction (tap, where the associated bit of a is 0; or rti, where bit 6 of the value loaded into the ccr from the stack has been cleared). there is no hardware action for clearing x. 3.1.6.8 stop disable (s) setting the stop disable (s) bit prevents the stop instruction from putting the m68hc11 into a low-power stop condition. if the stop instruction is encountered by the cpu while the s bit is set, it is treated as a no-operation (nop) instruction, and processing continues to the next instruction. s is set by reset stop disabled by de- fault. 3.2 data types the m68hc11 cpu supports the following data types: ? bit data ? 8-bit and 16-bit signed and unsigned integers ? 16-bit unsigned fractions ? 16-bit addresses a byte is eight bits wide and can be accessed at any byte location. a word is composed of two consecutive bytes with the most significant byte at the lower value address. be- cause the m68hc11 is an 8-bit cpu, there are no special requirements for alignment of instructions or operands. 3.3 opcodes and operands the m68hc11 family of microcontrollers uses 8-bit opcodes. each opcode identifies a particular instruction and associated addressing mode to the cpu. several opcodes are required to provide each instruction with a range of addressing capabilities. only 256 opcodes would be available if the range of values were restricted to the number able to be expressed in 8-bit binary numbers. a four-page opcode map has been implemented to expand the number of instructions. an additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. as its name implies, the additional byte precedes the opcode. a complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands. the operands contain information the cpu needs for executing the instruction. complete instructions can be from one to five bytes long. 3.4 addressing modes six addressing modes; immediate, direct, extended, indexed, inherent, and relative, detailed in the following paragraphs, can be used to access memory. all modes except inherent mode use an effective address. the effective address is the memory address from which the argument is fetched or stored, or the address from which execution is f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit technical data 3-7 to proceed. the effective address can be specified within an instruction, or it can be calculated. 3.4.1 immediate in the immediate addressing mode an argument is contained in the byte(s) immediate- ly following the opcode. the number of bytes following the opcode matches the size of the register or memory location being operated on. there are two-, three-, and four- (if prebyte is required) byte immediate instructions. the effective address is the ad- dress of the byte following the instruction. 3.4.2 direct in the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is as- sumed to be $00. addresses $00C$ff are thus accessed directly, using two-byte in- structions. execution time is reduced by eliminating the additional memory access required for the high-order address byte. in most applications, this 256-byte area is re- served for frequently referenced data. in m68hc11 mcus, the memory map can be configured for combinations of internal registers, ram or external memory to occupy these addresses. 3.4.2.1 extended in the extended addressing mode, the effective address of the argument is contained in two bytes following the opcode byte. these are three-byte instructions (or four-byte instructions if a prebyte is required). one or two bytes are needed for the opcode and two for the effective address. 3.4.2.2 indexed in the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in an index register (ix or iy) the sum is the effective address. this addressing mode allows referencing any memory location in the 64 kbyte address space. these are from two- to five-byte instructions, depending on whether or not a prebyte is required. 3.4.2.3 inherent in the inherent addressing mode, all the information necessary to execute the instruc- tion is contained in the opcode. operations that use only the index registers or accu- mulators, as well as control instructions with no arguments, are included in this addressing mode. these are one- or two-byte instructions. 3.4.2.4 relative the relative addressing mode is used only for branch instructions. if the branch con- dition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address. otherwise, control pro- ceeds to the next instruction. these are usually two-byte instructions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit 3-8 technical data 3.5 instruction set refer to table 3-2 , which shows all the m68hc11 instructions in all possible address- ing modes. for each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in cpu e-clock cycles. table 3-2 instruction set (sheet 1 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c aba add accumulators a + b t ainh1b2 d dddd abx add b to x ix + (00 : b) t ix inh 3a 3 aby add b to y iy + (00 : b) t iy inh 18 3a 4 adca (opr) add with carry to a a + m + c t a a imm adir a ext aind,x aind,y 89 99 b9 a9 18 a9 ii dd hh ll ff ff 2 3 4 4 5 d dddd adcb (opr) add with carry to b b + m + c t b b imm bdir b ext bind,x bind,y c9 d9 f9 e9 18 e9 ii dd hh ll ff ff 2 3 4 4 5 d dddd adda (opr) add memory to a a + m t a a imm adir a ext aind,x aind,y 8b 9b bb ab 18 ab ii dd hh ll ff ff 2 3 4 4 5 d dddd addb (opr) add memory to b b + m t bb imm bdir b ext bind,x bind,y cb db fb eb 18 eb ii dd hh ll ff ff 2 3 4 4 5 d dddd addd (opr) add 16-bit to d d + (m : m + 1) t dimm dir ext ind,x ind,y c3 d3 f3 e3 18 e3 jj kk dd hh ll ff ff 4 5 6 6 7 dddd anda (opr) and a with memory a ? m t a a imm a dir a ext aind,x aind,y 84 94 b4 a4 18 a4 ii dd hh ll ff ff 2 3 4 4 5 dd 0 andb (opr) and b with memory b ? m t b b imm bdir b ext bind,x bind,y c4 d4 f4 e4 18 e4 ii dd hh ll ff ff 2 3 4 4 5 dd 0 asl (opr) arithmetic shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 dddd asla arithmetic shift left a a inh 48 2 dddd aslb arithmetic shift left b b inh 58 2 dddd asld arithmetic shift left d inh 05 3 dddd asr arithmetic shift right ext ind,x ind,y 77 67 18 67 hh ll ff ff 6 6 7 dddd asra arithmetic shift right a a inh 47 2 dddd asrb arithmetic shift right b b inh 57 2 dddd bcc (rel) branch if carry clear ? c = 0 rel 24rr 3 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 c b7 b0 c b7 b0 c b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit technical data 3-9 bclr (opr) (msk) clear bit(s) m ? (mm) t mdir ind,x ind,y 15 1d 18 1d dd mm ff mm ff mm 6 7 8 dd 0 bcs (rel) branch if carry set ? c = 1 rel 25rr 3 beq (rel) branch if = zero ? z = 1 rel 27rr 3 bge (rel) branch if d zero ? n ? v = 0 rel 2crr 3 bgt (rel) branch if > zero ? z + (n ? v) = 0 rel 2err 3 bhi (rel) branch if higher ? c + z = 0 rel 22rr 3 bhs (rel) branch if higher or same ? c = 0 rel 24rr 3 bita (opr) bit(s) test a with memory a ? m a imm adir a ext aind,x aind,y 85 95 b5 a5 18 a5 ii dd hh ll ff ff 2 3 4 4 5 dd 0 bitb (opr) bit(s) test b with memory b ? m b imm bdir b ext bind,x bind,y c5 d5 f5 e5 18 e5 ii dd hh ll ff ff 2 3 4 4 5 dd 0 ble (rel) branch if d zero ? z + (n ? v) = 1 rel 2f rr 3 blo (rel) branch if lower ? c = 1 rel 25 rr 3 bls (rel) branch if lower or same ? c + z = 1 rel 23 rr 3 blt (rel) branch if < zero ? n ? v = 1 rel 2d rr 3 bmi (rel) branch if minus ? n = 1 rel 2b rr 3 bne (rel) branch if not = zero ? z = 0 rel 26 rr 3 bpl (rel) branch if plus ? n = 0 rel 2a rr 3 bra (rel) branch always ? 1 = 1 rel 20 rr 3 brclr(opr) (msk) (rel) branch if bit(s) clear ? m ? mm = 0 dir ind,x ind,y 13 1f 18 1f dd mm rr ff mm rr ff mm rr 6 7 8 brn (rel) branch never ? 1 = 0 rel 21 rr 3 brset(opr) (msk) (rel) branch if bit(s) set ? (m ) ? mm = 0 dir ind,x ind,y 12 1e 18 1e dd mm rr ff mm rr ff mm rr 6 7 8 bset (opr) (msk) set bit(s) m + mm t m dir ind,x ind,y 14 1c 18 1c dd mm ff mm ff mm 6 7 8 dd 0 bsr (rel) branch to subroutine see figure 3C2 rel 8d rr 6 bvc (rel) branch if overflow clear ? v = 0 rel 28 rr 3 bvs (rel) branch if overflow set ? v = 1 rel 29 rr 3 cba compare a to b a C b inh 11 2 dddd clc clear carry bit 0 t c inh 0c 2 0 cli clear interrupt mask 0 t i inh 0e 2 0 clr (opr) clear memory byte 0 t m ext ind,x ind,y 7f 6f 18 6f hh ll ff ff 6 6 7 0100 table 3-2 instruction set (sheet 2 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit 3-10 technical data clra clear accumulator a 0 t a a inh 4f 2 0100 clrb clear accumulator b 0 t b b inh 5f 2 0100 clv clear overflow flag 0 t v inh 0a 2 0 cmpa (opr) compare a to memory a C m a imm adir a ext aind,x aind,y 81 91 b1 a1 18 a1 ii dd hh ll ff ff 2 3 4 4 5 dddd cmpb (opr) compare b to memory b C m b imm bdir b ext bind,x bind,y c1 d1 f1 e1 18 e1 ii dd hh ll ff ff 2 3 4 4 5 dddd com (opr) ones complement memory byte $ff C m t m ext ind,x ind,y 73 63 18 63 hh ll ff ff 6 6 7 dd 01 coma ones complement a $ff C a t a a inh 43 2 dd 01 comb ones complement b $ff C b t b b inh 53 2 dd 01 cpd (opr) compare d to memory 16-bit d C m : m + 1 imm dir ext ind,x ind,y 1a 83 1a 93 1a b3 1a a3 cd a3 jj kk dd hh ll ff ff 5 6 7 7 7 dddd cpx (opr) compare x to memory 16-bit ix C m : m + 1 imm dir ext ind,x ind,y 8c 9c bc ac cd ac jj kk dd hh ll ff ff 4 5 6 6 7 dddd cpy (opr) compare y to memory 16-bit iy C m : m + 1 imm dir ext ind,x ind,y 18 8c 18 9c 18 bc 1a ac 18 ac jj kk dd hh ll ff ff 5 6 7 7 7 dddd daa decimal adjust a adjust sum to bcd inh 19 2 dddd dec (opr) decrement memory byte m C 1 t m ext ind,x ind,y 7a 6a 18 6a hh ll ff ff 6 6 7 ddd deca decrement accumulator a a C 1 t a a inh 4a 2 ddd decb decrement accumulator b b C 1 t b b inh 5a 2 ddd des decrement stack pointer sp C 1 t sp inh 34 3 dex decrement index register x ix C 1 t ix inh 09 3 d dey decrement index register y iy C 1 t iy inh 18 09 4 d eora (opr) exclusive or a with memory a ? m t aa imm adir a ext aind,x aind,y 88 98 b8 a8 18 a8 ii dd hh ll ff ff 2 3 4 4 5 dd 0 eorb (opr) exclusive or b with memory b ? m t bb imm bdir b ext bind,x bind,y c8 d8 f8 e8 18 e8 ii dd hh ll ff ff 2 3 4 4 5 dd 0 fdiv fractional divide 16 by 16 d / ix t ix; r t d inh 03 41 ddd idiv integer divide 16 by 16 d / ix t ix; r t d inh 02 41 d 0 d table 3-2 instruction set (sheet 3 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit technical data 3-11 inc (opr) increment memory byte m + 1 t m ext ind,x ind,y 7c 6c 18 6c hh ll ff ff 6 6 7 ddd inca increment accumulator a a + 1 t a a inh 4c 2 ddd incb increment accumulator b b + 1 t b b inh 5c 2 ddd ins increment stack pointer sp + 1 t sp inh 31 3 inx increment index register x ix + 1 t ix inh 08 3 d iny increment index register y iy + 1 t iy inh 18 08 4 d jmp (opr) jump see figure 3C2 ext ind,x ind,y 7e 6e 18 6e hh ll ff ff 3 3 4 jsr (opr) jump to subroutine see figure 3C2 dir ext ind,x ind,y 9d bd ad 18 ad dd hh ll ff ff 5 6 6 7 ldaa (opr) load accumulator a m t aaimm a dir a ext a ind,x a ind,y 86 96 b6 a6 18 a6 ii dd hh ll ff ff 2 3 4 4 5 dd 0 ldab (opr) load accumulator b m t bbimm b dir b ext b ind,x b ind,y c6 d6 f6 e6 18 e6 ii dd hh ll ff ff 2 3 4 4 5 dd 0 ldd (opr) load double accumulator d m t a,m + 1 t bimm dir ext ind,x ind,y cc dc fc ec 18 ec jj kk dd hh ll ff ff 3 4 5 5 6 dd 0 lds (opr) load stack pointer m : m + 1 t sp imm dir ext ind,x ind,y 8e 9e be ae 18 ae jj kk dd hh ll ff ff 3 4 5 5 6 dd 0 ldx (opr) load index register x m : m + 1 t ix imm dir ext ind,x ind,y ce de fe ee cd ee jj kk dd hh ll ff ff 3 4 5 5 6 dd 0 ldy (opr) load index register y m : m + 1 t iy imm dir ext ind,x ind,y 18 ce 18 de 18 fe 1a ee 18 ee jj kk dd hh ll ff ff 4 5 6 6 6 dd 0 lsl (opr) logical shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 dddd lsla logical shift left a a inh 48 2 dddd lslb logical shift left b b inh 58 2 dddd lsld logical shift left double inh 05 3 dddd lsr (opr) logical shift right ext ind,x ind,y 74 64 18 64 hh ll ff ff 6 6 7 0 ddd lsra logical shift right a a inh 44 2 0 ddd table 3-2 instruction set (sheet 4 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 c 0 b7 b0 c 0 b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit 3-12 technical data lsrb logical shift right b b inh 54 2 0 ddd lsrd logical shift right double inh 04 3 0 ddd mul multiply 8 by 8 a * b t d inh 3d 10 d neg (opr) twos complement memory byte 0 C m t m ext ind,x ind,y 70 60 18 60 hh ll ff ff 6 6 7 dddd nega twos complement a 0 C a t a a inh 40 2 dddd negb twos complement b 0 C b t b b inh 50 2 dddd nop no operation no operation inh 01 2 oraa (opr) or accumulator a (inclusive) a + m t a a imm adir a ext aind,x aind,y 8a 9a ba aa 18 aa ii dd hh ll ff ff 2 3 4 4 5 dd 0 orab (opr) or accumulator b (inclusive) b + m t b b imm bdir b ext bind,x bind,y ca da fa ea 18 ea ii dd hh ll ff ff 2 3 4 4 5 dd 0 psha push a onto stack a t stk,sp = sp C 1 a inh 36 3 pshb push b onto stack b t stk,sp = sp C 1 b inh 37 3 pshx push x onto stack (lo first) ix t stk,sp = sp C 2 inh 3c 4 pshy push y onto stack (lo first) iy t stk,sp = sp C 2 inh 18 3c 5 pula pull a from stack sp = sp + 1, a stka inh 32 4 pulb pull b from stack sp = sp + 1, b stkb inh 33 4 pulx pull x from stack (hi first) sp = sp + 2, ix stk inh 38 5 puly pull y from stack (hi first) sp = sp + 2, iy stk inh 18 38 6 rol (opr) rotate left ext ind,x ind,y 79 69 18 69 hh ll ff ff 6 6 7 dddd rola rotate left a a inh 49 2 dddd rolb rotate left b b inh 59 2 dddd ror (opr) rotate right ext ind,x ind,y 76 66 18 66 hh ll ff ff 6 6 7 dddd rora rotate right a a inh 46 2 dddd rorb rotate right b b inh 56 2 dddd rti return from interrupt see figure 3C2 inh 3b 12 ddddddd rts return from subroutine see figure 3C2 inh 39 5 sba subtract b from a a C b t a inh 10 2 dddd table 3-2 instruction set (sheet 5 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c c 0 b7 b0 c 0 b7 b0 a b b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit technical data 3-13 sbca (opr) subtract with carry from a a C m C c t a a imm adir a ext aind,x aind,y 82 92 b2 a2 18 a2 ii dd hh ll ff ff 2 3 4 4 5 dddd sbcb (opr) subtract with carry from b b C m C c t b b imm bdir b ext bind,x bind,y c2 d2 f2 e2 18 e2 ii dd hh ll ff ff 2 3 4 4 5 dddd sec set carry 1 t c inh 0d 2 1 sei set interrupt mask 1 t i inh 0f 2 1 sev set overflow flag 1 t v inh 0b 2 1 staa (opr) store accumulator a a t madir a ext aind,x aind,y 97 b7 a7 18 a7 dd hh ll ff ff 3 4 4 5 dd 0 stab (opr) store accumulator b b t mbdir b ext bind,x bind,y d7 f7 e7 18 e7 dd hh ll ff ff 3 4 4 5 dd 0 std (opr) store accumulator d a t m, b t m + 1 dir ext ind,x ind,y dd fd ed 18 ed dd hh ll ff ff 4 5 5 6 dd 0 stop stop internal clocks inh cf 2 sts (opr) store stack pointer sp t m : m + 1 dir ext ind,x ind,y 9f bf af 18 af dd hh ll ff ff 4 5 5 6 dd 0 stx (opr) store index register x ix t m : m + 1 dir ext ind,x ind,y df ff ef cd ef dd hh ll ff ff 4 5 5 6 dd 0 sty (opr) store index register y iy t m : m + 1 dir ext ind,x ind,y 18 df 18 ff 1a ef 18 ef dd hh ll ff ff 5 6 6 6 dd 0 suba (opr) subtract memory from a a C m t a a imm adir a ext aind,x aind,y 80 90 b0 a0 18 a0 ii dd hh ll ff ff 2 3 4 4 5 dddd subb (opr) subtract memory from b b C m t b a imm adir a ext aind,x aind,y c0 d0 f0 e0 18 e0 ii dd hh ll ff ff 2 3 4 4 5 dddd subd (opr) subtract memory from d d C m : m + 1 t dimm dir ext ind,x ind,y 83 93 b3 a3 18 a3 jj kk dd hh ll ff ff 4 5 6 6 7 dddd swi software interrupt see figure 3C2 inh 3f 14 1 tab transfer a to b a t b inh 16 2 dd 0 tap transfer a to cc register a t ccr inh 06 2 ddddddd tba transfer b to a b t a inh 17 2 dd 0 test test (only in test modes) address bus counts inh 00 * tpa transfer cc register to a ccr t a inh 07 2 tst (opr) test for zero or minus m C 0 ext ind,x ind,y 7d 6d 18 6d hh ll ff ff 6 6 7 dd 00 tsta test a for zero or minus a C 0 a inh 4d 2 dd 00 tstb test b for zero or minus b C 0 b inh 5d 2 dd 00 table 3-2 instruction set (sheet 6 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit 3-14 technical data tsx transfer stack pointer to x sp + 1 t ix inh 30 3 tsy transfer stack pointer to y sp + 1 t iy inh 18 30 4 txs transfer x to stack pointer ix C 1 t sp inh 35 3 tys transfer y to stack pointer iy C 1 t sp inh 18 35 4 wai wait for interrupt stack regs & wait inh 3e ** xgdx exchange d with x ix t d, d t ix inh 8f 3 xgdy exchange d with y iy t d, d t iy inh 18 8f 4 table 3-2 instruction set (sheet 7 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory technical data 4-1 section 4 operating modes and on-chip memory this section contains information about the modes that define MC68HC11d3 operat- ing conditions, and about the on-chip memory that allows the mcu to be configured for various applications. 4.1 operating modes the values of the mode select inputs modb and moda during reset determine the operating mode. single chip and expanded multiplexed are the normal modes. with single-chip mode only on-board memory is available. expanded multiplexed mode, however, allows access to external memory. each of these two normal modes is paired with a special mode. bootstrap, a variation of the single-chip mode, is a special mode that executes a bootloader program in an internal bootstrap rom. test is a spe- cial mode that allows privileged access to internal resources. 4.1.1 single-chip mode in single-chip mode, ports b and c are available for general-purpose parallel i/o. in expanded multiplexed mode the mcu can access a 64 kbyte address space. the total address space includes the same on-chip memory addresses used for single-chip mode plus external memory and peripheral devices. 4.1.2 expanded multiplexed mode expanded memory access is achieved by providing multiplexed external data and ad- dress buses on two of the m68hc11 ports; therefore only 18 pins are needed for an 8-bit data bus, a 16-bit address bus and two bus control lines. port b is designated for addr[15:8], while port c is multiplexed addr[7:0]/data[7:0]. the address, r/w , and as signals are active and valid for all bus cycles including accesses to internal memory locations. refer to figure 4-1 , which illustrates a recommended method of demultiplexing low order addresses from data at port c. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory 4-2 technical data figure 4-1 address/data demultiplexing 4.1.3 special test mode special test, a variation of the expanded multiplexed mode, is primarily used during motorola's internal production testing; however, it is accessible for programming the config register, and supporting emulation and debugging during development. 4.1.4 bootstrap mode when the mcu is reset in special bootstrap mode, a small amount of on-chip rom is enabled at address $bf00C$bfff. the rom contains a bootloader program and a special set of interrupt and reset vectors. the mcu fetches the reset vector, then ex- ecutes the bootloader. for normal use of the bootloader program, send $ff to the sci receiver at either e clock ? 16, or e clock ? 104 (1200 baud for e clock equals 2 mhz). then download up to 192 bytes of program data, which is put into ram starting at $0040. these charac- ters are echoed through the transmitter. when loading is complete, the program jumps to location $0040 and begins executing the code. the bootloader program ends the download after 192 bytes, or when the received data line is idle for at least four char- acter times. use of an external pullup resistor is required when using the sci transmit- ter pin because port d pins are configured for wired-or operation by the bootloader. in bootstrap mode, the interrupt vectors are directed to ram. this allows the use of interrupts through a jump table. refer to freescale application note an1060, MC68HC11 bootstrap mode. hc373 mcu addr/data demux addr14 addr13 addr12 addr11 addr10 addr9 addr8 addr15 addr6 addr5 addr4 addr3 addr2 addr1 addr0 addr7 data6 data5 data4 data3 data2 data1 data0 data7 d2 d3 d4 d5 d6 d7 d8 d1 q2 q3 q4 q5 q6 q7 q8 q1 oe le pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc7 as pb6 pb5 pb4 pb3 pb2 pb1 pb0 pb7 r/w e we oe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory technical data 4-3 4.2 memory map the operating mode determines memory mapping and whether memory is addressed on- or off-chip. refer to figure 4-2 , which illustrates the memory maps for each of the four modes of operation. memory locations for on-chip resources are the same for both expanded multiplexed and single-chip modes. 192-byte ram is mapped to $0040 af- ter reset. it can be placed at any other 4k boundary ($x040) by writing an appropriate value to the init register. the 64-byte register block is mapped to $0000 after reset and can also be placed at any 4k boundary ($x000) by writing an appropriate value to the init register. refer to table 4-1 , which details the mcu register and control bit assignments. figure 4-2 MC68HC11d3 memory map single chip bootstrap special test expanded normal modes interrupt vectors 192 bytes static ram 64-byte register block $0000 $0040 $7000 $f000 $ffff special modes interrupt vectors 4 kbytes rom 4 kbytes rom boot rom d3 mem map ffc0 ffff bfc0 bfff ffff bf00 bfff 7000 7fff 0040 00ff 0000 003f ext ext f000 ffff ext f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory 4-4 technical data table 4-1 register and control bit assignments bit 7654321bit 0 $0000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta $0001 reserved $0002 cwom pioc $0003 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portc $0004 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb $0005 reserved $0006 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb $0007 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc $0008 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 portd $0009 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd $000a reserved $000b foc1 foc2 foc3 foc4 foc5 0 0 0 cforc $000c oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 oc1m $000d oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 oc1d $000e bit 15 14 13 12 11 10 9 bit 8 tcnt (high) $000fbit 7654321bit 0tcnt (low) $0010 bit 15 14 13 12 11 10 9 bit 8 tic1 (high) $0011bit 7654321bit 0tic1 (low) $0012 bit 15 14 13 12 11 10 9 bit 8 tic2 (high) $0013bit 7654321bit 0tic2 (low) $0014 bit 15 14 13 12 11 10 9 bit 8 tic3 (high) $0015bit 7654321bit 0tic3 (low) $0016 bit 15 14 13 12 11 10 9 bit 8 toc1(high) $0017bit 7654321bit 0toc1 (low) $0018 bit 15 14 13 12 11 10 9 bit 8 toc2 (high) $0019bit 7654321bit 0toc2 (low) $001a bit 15 14 13 12 11 10 9 bit 8 toc3 (high) $001bbit 7654321bit 0toc3 (low) $001c bit 15 14 13 12 11 10 9 bit 8 toc4 (high) $001dbit 7654321bit 0toc4 (low) $0023 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f tflg1 $0024 toi rtii paovi paii 0 0 pr1 pr0 tmsk2 $0025tofrtifpaovfpaif0000tflg2 $0026 ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 pactl $0027bit 7654321bit 0pacnt $0028 spie spe dwom mstr cpol cpha spr1 spr0 spcr $0029spifwcol0modf0000 spsr $002abit 7654321bit 0spdr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory technical data 4-5 the bootloader program is contained in the 192-byte bootstrap rom. this rom, which appears as internal memory space at locations $bf40C$bfff, is enabled only if the mcu is reset in special bootstrap mode. memory locations are the same for expanded multiplexed and single-chip modes, ex- cept for rom in expanded mode and the bootloader rom in special bootstrap mode. the on-board 192-byte ram is initially located at $0040 after reset, but can be placed at any other 4k boundary ($x040) by writing an appropriate value to the init register. the 4 kbyte rom is located at $f000 through $ffff in all modes except expanded multiplexed, in which it is located at $7000. rom can be located at $f000 in expanded multiplexed by entering single-chip mode out of reset and setting the mda bit in the hprio register to 1, thereby entering expanded mode from internal rom. disable rom by clearing the romon bit in the config register. hardware priority is built into ram and i/o remapping. registers and ram have prior- ity over rom. in the event of conflicts, the higher priority resource takes precedence. the 192 bytes of fully static ram store instructions, variables, and temporary data. the direct addressing mode can access ram locations using a one-byte address op- erand, saving program memory space and execution time, depending on the applica- tion. ram contents are preserved during periods of processor inactivity by two methods, both of which reduce power consumption. in the software-based stop mode, the clocks are stopped while v dd powers the mcu. because power supply current is directly related to operating frequency in cmos integrated circuits, only a very small amount of leakage exists when the clocks are stopped. $002b tclr 0 scp1 scp0 rckb scr2 scr1 scr0 baud $002c r8 t8 0 m wake 0 0 0 sccr1 $002d tie tcie rie ilie te re rwu sbk sccr2 $002e tdre tc rdrf idle or nf fe 0 scsr $002f r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 scdr $0030 reserved to $0038 reserved $0039 0 0 irqe dly cme 0 cr1 cr0 option $003abit 7654321bit 0coprst $003b reserved $003c rboot smod mda irvne psel3 psel2 psel1 psel0 hprio $003d ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 init $003e tilop 0 occr cbyp disr fcm fcop 0 test1 $003f00000nocopromon0config table 4-1 register and control bit assignments (continued) bit 7654321bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory 4-6 technical data in the second method, the modb/v stby pin can supply ram power from a battery backup or from a second power supply, as shown in figure 4-3 . using the modb/ v stby pin may require external hardware, but can be justified when a significant amount of external circuitry is operating from v dd . if v stby is used to maintain ram contents, reset must be held low whenever v dd is below normal operating level. refer to section 5 resets and interrupts . figure 4-3 ram standby modb/v stby connections 4.2.1 priority and mode select register the four operating modes are selected with the logic states of the mode a (moda) and mode b (modb) pins during reset. the moda and modb logic levels determine the logic state of the special mode (smod) and mode a (mda) control bits in the hprio register. after reset is released, the mode select pins no longer influence the mcu operating mode. for single-chip mode, the moda pin is connected to a logic zero. for expanded mode, moda is normally connected to v dd through a pull-up resistor of 4.7 k w. the moda pin also functions as the load instruction register (lir ) pin when the mcu is not in reset. the open drain active low lir output pin drives low during the first e cycle of each instruction. the modb pin also functions as standby power input, v stby, which maintains ram contents in the absence of v dd . refer to table 4-2 for information about hardware mode selection. table 4-2 hardware mode select summary inputs mode latched at reset modb moda rboot smod mda 1 0 single-chip 0 0 0 1 1 expanded multiplexed 0 0 1 0 0 special bootstrap 1 1 0 0 1 special test 0 1 1 modb/vstby conn 4.7k max 690 v batt + 4.8 v nicd v dd v dd v out to modb/v stby of m68hc11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory technical data 4-7 the values of the rboot, smod, irvne, and mda at reset depend on the mode dur- ing initialization. refer to table 4-2 . rboot read bootstrap rom has meaning only when the smod bit is a one (special bootstrap mode or special test mode). at all other times this bit is clear and cannot be written. 0 = bootloader rom disabled and not in map 1 = bootloader rom enabled and located in map at $bf40C$bfff smod special mode select this bit reflects the inverse of the modb input pin at the rising edge of reset. it is set if the modb input pin is low during reset. if modb is high during reset, it is cleared. smod can be cleared under software control from the special modes, thus changing the operating mode of the mcu. smod can never be set by software. 0 = normal mode variation in effect 1 = special mode variation in effect mda mode select a the mode select a bit reflects the status of the moda input pin at the rising edge of reset. while the smod bit is set (special bootstrap or special test mode in effect), the mda bit can be written, thus changing the operating mode of the mcu. when the smod bit is clear, the moda bit is read-only and the operating mode cannot be changed without going through a reset sequence. 0 = normal single-chip or special bootstrap mode in effect 1 = normal expanded or special test mode in effect irvne internal read visibility/not e the irvne control bit allows internal read accesses to be available on the external data bus during factory testing or emulation. if this capability is used for other purpos- es, bus conflicts can occur because the bidirectional data bus is driven out during a read of internal addresses, even though the r/w line suggests a high impedance read mode. 0 = no internal read visibility on external bus 1 = internal read data driven out data bus in single-chip modes, this bit determines whether the e clock drives out of the chip. 0 = e driven out 1 = e pin driven low hprio highest priority i-bit interrupt and miscellaneous $003c bit 7654321bit 0 rboot smod mda irvne psel3 psel2 psel1 psel0 reset: 0101 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory 4-8 technical data psel[3:0] priority select bits refer to section 5 resets and interrupts . 4.2.2 system initialization registers and bits that control initialization and the basic configuration of the mcu are protected against writes except under special circumstances. the protection mecha- nism, overridden in special operating modes, permits writing these bits only within the first 64 bus cycles after any reset, and then only once after each reset. if the mcu is going to be changed to a normal mode after being reset in a special mode, write to the protected registers before writing the smod control bit to zero. 4.2.2.1 config register the config register consists of static latches that control the startup configuration of the mcu. config is writable only once in expanded and single-chip modes (smod = 0). in these modes, the cop watchdog timer is enabled out of reset. bits [7:3] and 0 not implemented always read zero nocop cop system disable this bit is cleared out of reset in normal modes (cop enabled). refer to section 5 resets and interrupts . 0 = cop system enabled 1 = cop system disabled romon rom enable in all modes, romon is forced to one out of reset. writable once in normal modes and writable at any time in special modes. 0 = rom removed from the memory map 1 = rom present in the memory map mode irvne out of reset e clock out of reset irv out of reset irvne affects only single-chip 0 on off e expanded 0 on off irv boot 0 on off e special test 1 on on irv config system configuration $003f bit 7654321bit 0 00000nocopromon0 reset:00000 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory technical data 4-9 note in expanded mode, rom is located at $7000C$7fff out of reset. in all other modes, rom is located at $f000C$ffff. 4.2.2.2 init register the internal registers used to control the operation of the mcu can be relocated on 4k boundaries within the memory space with the use of init. this 8-bit special-purpose register can change the default locations of the ram and control registers within the mcu memory map. it can be written to only once within the first 64 e-clock cycles after a reset, and then it becomes a read-only register. ram[3:0] ram map position these four bits, which specify the upper hexadecimal digit of the ram address, control position of ram in the memory map. ram can be positioned at the beginning of any 4k page in the memory map. it is initialized to address $0040 out of reset. refer to table 4-3 . reg[3:0] 64-byte register block position these four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal registers. the register block, positioned at the beginning of any 4k page in the memory map, is initialized to address $0000 out of reset. refer to table 4-4 . init ram and i/o mapping register $003d bit 7654321bit 0 ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 reset:00000001 table 4-3 ram mapping table 4-4 register mapping ram[3:0] address reg[3:0] address 0000 $0040C$00ff 0000 $0000C$003f 0001 $1040C$10ff 0001 $1000C$103f 0010 $2040C$20ff 0010 $2000C$203f 0011 $3040C$30ff 0011 $3000C$303f 0100 $4040C$40ff 0100 $4000C$403f 0101 $5040C$50ff 0101 $5000C$503f 0110 $6040C$60ff 0110 $6000C$603f 0111 $7040C$70ff 0111 $7000C$703f 1000 $8040C$80ff 1000 $8000C$803f 1001 $9040C$90ff 1001 $9000C$903f 1010 $a040C$a0ff 1010 $a000C$a03f 1011 $b040C$b0ff 1011 $b000C$b03f 1100 $c040C$c0ff 1100 $c000C$c03f 1101 $d040C$d0ff 1101 $d000C$d03f 1110 $e040C$e0ff 1110 $e000C$e03f 1111 $f040C$f0ff 1111 $f000C$f03f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory 4-10 technical data 4.2.2.3 option register the 8-bit special-purpose option register sets internal system configuration options during initialization. the time protected control bits, irqe, dly, and cr[1:0] can be written to only once after a reset and then they become read-only. this minimizes the possibility of any accidental changes to the system configuration. *can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes bits [7:6] and 2 not implemented always read zero irqe irq select edge sensitive only 0 = irq is configured for level sensitive operation 1 = irq is configured for edge sensitive only operation dly enable oscillator startup delay 0 = the oscillator startup delay coming out of stop is bypassed and the mcu re- sumes processing within about four bus cycles. 1 = a delay of approximately 4000 e-clock cycles is imposed as the mcu is started up from the stop power-saving mode. this delay allows the crystal oscillator to stabilize. cme clock monitor enable refer to section 5 resets and interrupts . cr[1:0] cop timer rate select bits the internal e clock is first divided by 2 15 before it enters the cop watchdog system. these control bits determine a scaling factor for the watchdog timer. refer to sec- tion 5 resets and interrupts . option system configuration options $0039 bit 7654321bit 0 0 0 irqe* dly* cme 0 cr1* cr0* reset:00010000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts technical data 5-1 section 5 resets and interrupts resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. a reset immediately stops execution of the current instruction and forces the program counter to a known starting address. internal registers and control bits are initialized so the mcu can resume ex- ecuting instructions. an interrupt temporarily suspends normal program execution while an interrupt service routine is being executed. after an interrupt has been ser- viced, the main program resumes as if there had been no interruption. 5.1 resets there are four possible sources of reset. power-on reset (por) and external reset share the normal reset vector. the computer operating properly (cop) system and the clock monitor each has its own vector. 5.1.1 power-on reset a positive transition on v dd generates a power-on reset (por), which is used only for power-up conditions. por cannot be used to detect drops in power supply voltages. a 4064 t cyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. if reset is at logical zero at the end of 4064 t cyc , the cpu remains in the reset condition until goes to logical one. it is important to protect the mcu during power transitions. most m68hc11 systems need an external circuit that holds the reset pin low whenever v dd is below the min- imum operating level. this external voltage level detector, or other external reset cir- cuits, are the usual source of reset in a system. the por circuit only initializes internal circuitry during cold starts. refer to figure 2-3 . 5.1.2 external reset (reset ) the cpu distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic one in less than two e-clock cycles after an inter- nal device releases reset. when a reset condition is sensed, the reset pin is driven low by an internal device for four e-clock cycles, then released. two e-clock cycles later it is sampled. if the pin is still held low, the cpu assumes that an external reset has occurred. if the pin is high, it indicates that the reset was initiated internally by ei- ther the cop system or the clock monitor. it is not advisable to connect an external resistor capacitor (rc) power-up delay circuit to the reset pin of m68hc11 devices be- cause the circuit charge time constant can cause the device to misinterpret the type of reset that occurred. 5.1.3 cop reset the mcu includes a cop system to help protect against software failures. when the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts 5-2 technical data cop is enabled, the software is responsible for keeping a free-running watchdog timer from timing out. when the software is no longer being executed in the intended se- quence, a system reset is initiated. the state of the nocop bit in the config register determines whether the cop sys- tem is enabled or disabled. in normal modes, cop is enabled out of reset and does not depend on software action. to disable the cop system, set the nocop bit in the config register. in the special test and bootstrap operating modes, the cop system is initially inhibited by the disable resets (disr) control bit in the test1 register. the disr bit can subsequently be written to zero to enable cop resets. the cop timer rate control bits cr[1:0] in the option register determine the cop time-out period. the system e clock is divided by 2 15 and then further scaled by a fac- tor shown in table 5-1 . after reset, these bits are zero, which selects the fastest time- out period. in normal operating modes, these bits can only be written once within 64 bus cycles after reset. complete the following reset sequence to service the cop timer. write $55 to co- prst to arm the cop timer clearing mechanism. then write $aa to coprst to clear the cop timer. performing instructions between these two steps is possible as long as both steps are completed in the correct sequence before the timer times out. 5.1.4 clock monitor reset the clock monitor circuit is based on an internal rc time delay. if no mcu clock edges are detected within this rc time delay, the clock monitor can optionally generate a sys- tem reset. the clock monitor function is enabled or disabled by the cme control bit in the option register. the presence of a time-out is determined by the rc delay, which allows the clock monitor to operate without any mcu clocks. clock monitor is used as a backup for the cop system. because the cop needs a clock to function, it is disabled when the clocks stop. therefore, the clock monitor sys- tem can detect clock failures not detected by the cop system. table 5-1 cop time-out cr[1:0] divide e/2 15 by xtal = 4.0 mhz time-out C0/+32.8 ms xtal = 8.0 mhz time-out C0/+16.4 ms xtal = 12.0 mhz time-out C0/+10.9 ms 0 0 1 32.768 ms 16.384 ms 10.923 ms 0 1 4 131.072 ms 65.536 ms 43.691 ms 1 0 16 524.288 ms 262.140 ms 174.76 ms 1 1 64 2.097 sec 1.049 sec 699.05 ms e = 1.0 mhz 2.0 mhz 3.0 mhz coprst am/reset cop timer circuitry $003a bit 7654321bit 0 76543210 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts technical data 5-3 semiconductor wafer processing causes variations of the rc time-out values between individual devices. an e-clock frequency below 10 khz is detected as a clock monitor error. an e-clock frequency of 200 khz or more prevents clock monitor errors. using the clock monitor function when the e clock is below 200 khz is not recommended. special considerations are needed when a stop instruction is executed and the clock monitor is enabled. because the stop function causes the clocks to be halted, the clock monitor function generates a reset sequence if it is enabled at the time the stop mode was initiated. before executing a stop instruction, clear the cme bit in the op- tion register to zero to disable the clock monitor. after recovery from stop, set the cme bit to logic one to enable the clock monitor. 5.1.5 option register *can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. bits [7:6] and 2 not implemented always read zero irqe configure irq for edge sensitive only operation this bit can be written only once during the first 64 e-clock cycles after reset in normal modes. 0 = low level recognition 1 = falling edge recognition dly enable oscillator startup delay this bit is set during reset and can be written only once during the first 64 e-clock cy- cles after reset in normal modes. if an external clock source rather than a crystal is used, the stabilization delay can be inhibited because the clock source is assumed to be stable. 0 = no stabilization delay on exit from stop 1 = stabilization delay enabled on exit from stop cme clock monitor enable this control bit can be read or written at any time and controls whether or not the in- ternal clock monitor circuit triggers a reset sequence when the system clock is slow or absent. when it is clear, the clock monitor circuit is disabled. when it is set, the clock monitor circuit is enabled. reset clears the cme bit. cr[1:0] cop timer rate select these control bits determine a scaling factor for the watchdog timer. option system configuration options $0039 bit 7654321bit 0 0 0 irqe* dly* cme 0 cr1* cr0* reset:00010000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts 5-4 technical data 5.1.6 config register bits [7:4] and 0 not implemented always read zero nocop cop system disable this bit is cleared out of reset in normal modes, enabling the cop system. it is set out of reset in special modes. nocop is writable once in normal modes and at any time in special modes. 0 = the cop system is enabled as the mcu comes out of reset. 1 = the cop system is disabled and does not generate system resets. romon enable on-chip rom refer to section 4 operating modes and on-chip memory . 5.2 effects of reset when a reset condition is recognized, the internal registers and control bits are forced to an initial state. depending on the cause of the reset and the operating mode, the reset vector can be fetched from any of six possible locations. refer to table 5-2 . these initial states then control on-chip peripheral systems to force them to known startup states, as follows: 5.2.1 cpu after reset, the cpu fetches the restart vector from the appropriate address during the first three cycles, and begins executing instructions. the stack pointer and other cpu registers are indeterminate immediately after reset; however, the x and i interrupt mask bits in the condition code register (ccr) are set to mask any interrupt requests. also, the s bit in the ccr is set to inhibit the stop mode. 5.2.2 memory map after reset, the init register is initialized to $00, putting the 192 bytes of ram at loca- tions $0040 through $00ff, and the control registers at locations $0000 through $003f. config configuration control register $003f bit 7654321bit 0 00000nocopromon0 reset:00000 0 table 5-2 reset cause, reset vector, and operating mode cause of reset normal mode vector special test or bootstrap por or reset pin $fffe, ffff $bffe, bfff clock monitor failure $fffc, fffd $bffc, $bffd cop watchdog time-out $fffa, fffb $bffa, bffb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts technical data 5-5 5.2.3 parallel i/o when a reset occurs in expanded multiplexed operating modes, the pins used for par- allel i/o are dedicated to the expansion bus. in single-chip and bootstrap modes, all ports are parallel i/o data ports. in expanded multiplexed and test modes, ports b, c, and lines data6/as and data7/r/w are a memory expansion bus with port b as a high-order address bus, port c as a multiplexed address and data bus, as as the de- multiplexing signal, and r/as the data bus direction control. the cwom bit in pioc is cleared so that port c is not in wired-or mode. port a, bits [0:3] and 7; and ports b, c, and d are general-purpose i/o at reset and set for input. for this reason the pins are configured as high impedance upon reset. port a bits [4:6] are outputs, so high im- pedance protection is not necessary. note do not confuse pin function with the electrical state of the pin at reset. all general-purpose i/o pins configured as inputs at reset are in a high impedance state. port data registers reflect the port's functional state at reset. the pin function is mode dependent. 5.2.4 timer during reset, the timing system is initialized to a count of $0000. the prescaler bits are cleared, and all output compare registers are initialized to $ffff. all input capture reg- isters are indeterminate after reset. the output compare 1 mask (oc1m) register is cleared so that successful oc1 compares do not affect any i/o pins. the other four output compares are configured so that they do not affect any i/o pins on successful compares. all input capture edge-detector circuits are configured for capture disabled operation. the timer overflow interrupt flag and all eight timer function interrupt flags are cleared. all nine timer interrupts are disabled because their mask bits have been cleared. the i4/o5 bit in the pactl register is cleared to configure the i4/o5 function as oc5; however, the om5:ol5 control bits in the tctl1 register are clear so oc5 does not control the pa3 pin. 5.2.5 real-time interrupt the real-time interrupt flag (rtif) is cleared and automatic hardware interrupts are masked. the rate control bits are cleared after reset and can be initialized by software before the real-time interrupt (rti) system is used. after reset, a full rti period elaps- es before the first rti interrupt. 5.2.6 pulse accumulator the pulse accumulator system is disabled at reset so that the pai input pin defaults to being a general-purpose input pin (pa7). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts 5-6 technical data 5.2.7 cop the cop watchdog system is enabled if the nocop control bit in the config regis- ter is clear, and disabled if nocop is set. the cop rate is set for the shortest duration time-out. 5.2.8 sci the reset condition of the sci system is independent of the operating mode. at reset, the sci baud rate is indeterminate and must be established by a software write to the baud register. all transmit and receive interrupts are masked and both the transmitter and receiver are disabled so the port pins default to being general-purpose i/o lines. the sci frame format is initialized to an 8-bit character size. the send break and re- ceiver wake-up functions are disabled. the tdre and tc status bits in the sci status register are both set, indicating that there is no transmit data in either the transmit data register or the transmit serial shift register. the rdrf, idle, or, nf, and fe receive- related status bits are cleared. 5.2.9 spi the spi system is disabled by reset. the port pins associated with this function default to being general-purpose i/o lines. 5.2.10 system the memory system is configured for normal read operation. psel[3:0] are initialized with the value $0101, causing the external irq pin to have the highest i-bit interrupt priority. the irq pin is configured for level sensitive operation (for wired-or systems). the rboot, smod, and mda bits in the hprio register reflect the status of the modb and moda inputs at the rising edge of reset. the dly control bit in option is set to specify that an oscillator start-up delay is imposed upon recovery from stop. the clock monitor system is disabled by cme equals zero. 5.3 reset and interrupt priority resets and interrupts have a hardware priority that determines which reset or interrupt is serviced first when simultaneous requests occur. any maskable interrupt can be giv- en priority over other maskable interrupts. the first six interrupt sources are not maskable. the priority arrangement for these sources is as follows: 1. por or reset pin 2. clock monitor reset 3. cop watchdog reset 4. xirq interrupt 5. illegal opcode interrupt 6. software interrupt (swi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts technical data 5-7 the maskable interrupt sources have the following priority arrangement: 1. irq 2. real-time interrupt 3. timer input capture 1 4. timer input capture 2 5. timer input capture 3 6. timer output compare 1 7. timer output compare 2 8. timer output compare 3 9. timer output compare 4 10. timer input capture 4/output compare 5 11. timer overflow 12. pulse accumulator overflow 13. pulse accumulator input edge 14. spi transfer complete 15. sci system any one of these interrupts can be assigned the highest maskable interrupt priority by writing the appropriate value to the psel bits in the hprio register. otherwise, the priority arrangement remains the same. an interrupt that is assigned highest priority is still subject to global masking by the i bit in the ccr, or by any associated local bits. interrupt vectors are not affected by priority assignment. to avoid race conditions, hprio can be written only while i-bit interrupts are inhibited. 5.3.1 highest priority interrupt and miscellaneous register the values of the rboot, smod, irvne, and mda reset bits depend on the mode during initialization. refer to table 5-3 . rboot read bootstrap rom has meaning only when the smod bit is a one (special bootstrap mode or special test mode). at all other times this bit is clear and cannot be written. refer to section 4 operating modes and on-chip memory for more information. smod special mode select this bit reflects the inverse of the modb input pin at the rising edge of reset. refer to section 4 operating modes and on-chip memory for more information. mda mode select a the mode select a bit reflects the status of the moda input pin at the rising edge of reset. refer to section 4 operating modes and on-chip memory for more information. irvne internal read visibility enable/not e hprio highest priority i-bit interrupt and miscellaneous $003c bit 7654321bit 0 rboot smod mda irvne psel3 psel2 psel1 psel0 reset: 0101 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts 5-8 technical data the irvne control bit allows internal read accesses to be available on the external data bus during factory testing or emulation. refer to section 4 operating modes and on-chip memory for more information. psel[3:0] priority select bits these bits select one interrupt source to be elevated above all other i-bit-related sources and can be written to only while the i bit in the ccr is set (interrupts disabled). 5.4 interrupts the mcu has 18 interrupt vectors that support 22 interrupt sources. the 19 maskable interrupts are generated by on-chip peripheral systems. these interrupts are recog- nized when the global interrupt mask bit (i) in the condition code register (ccr) is clear. the three non-maskable interrupt sources are illegal opcode trap, software in- terrupt, and xirq pin. refer to table 5-4 , which shows the interrupt sources and vec- tor assignments for each source. table 5-3 highest priority interrupt selection psel[3:0] interrupt source promoted 0 0 0 0 timer overflow 0 0 0 1 pulse accumulator overflow 0 0 1 0 pulse accumulator input edge 0 0 1 1 spi serial transfer complete 0 1 0 0 sci serial system 0 1 0 1 reserved (default to irq ) 0 1 1 0 irq (external pin) 0 1 1 1 real-time interrupt 1 0 0 0 timer input capture 1 1 0 0 1 timer input capture 2 1 0 1 0 timer input capture 3 1 0 1 1 timer output compare 1 1 1 0 0 timer output compare 2 1 1 0 1 timer output compare 3 1 1 1 0 timer output compare 4 1 1 1 1 timer input capture 4/output compare 5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts technical data 5-9 5.4.1 interrupt recognition and register stacking an interrupt can be recognized at any time after it is enabled by its local mask, if any, and by the global mask bit in the ccr. once an interrupt source is recognized, the cpu responds at the completion of the instruction being executed. interrupt latency varies according to the number of cycles required to complete the current instruction. when the cpu begins to service an interrupt, the contents of the cpu registers are pushed onto the stack in the order shown in table 5-5 . after the ccr value is stacked, the i bit and the x bit, if xirq is pending, are set to inhibit further interrupts. the inter- rupt vector for the highest priority pending source is fetched, and execution continues at the address specified by the vector. at the end of the interrupt service routine, the return from interrupt instruction is executed and the saved registers are pulled from the stack in reverse order so that normal program execution can resume. refer to sec- tion 3 central processing unit for further information. table 5-4 interrupt and reset vector assignments vector address interrupt source ccr mask local mask ffc0, c1 ffd4, d5 reserved ffd6, d7 sci serial system i bit sci transmit complete tcie sci transmit data register empty tie sci idle line detect ilie sci receiver overrun rie sci receive data register full rie ffd8, d9 spi serial transfer complete i bit spie ffda, db pulse accumulator input edge i bit paii ffdc, dd pulse accumulator overflow i bit paovi ffde, df timer overflow i bit toi ffe0, e1 timer input capture 4/output compare 5 i bit i4/o5i ffe2, e3 timer output compare 4 i bit oc4i ffe4, e5 timer output compare 3 i bit oc3i ffe6, e7 timer output compare 2 i bit oc2i ffe8, e9 timer output compare 1 i bit oc1i ffea, eb timer input capture 3 i bit ic3i ffec, ed timer input capture 2 i bit ic2i ffee, ef timer input capture 1 i bit ic1i fff0, f1 real time interrupt i bit rtii fff2, f3 irq (external pin) i bit none fff4, f5 xirq pin x bit none fff6, f7 software interrupt none none fff8, f9 illegal opcode trap none none fffa, fb cop failure none nocop fffc, fd clock monitor fail none cme fffe, ff reset none none f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts 5-10 technical data 5.4.2 non-maskable interrupt request xirq non-maskable interrupts are useful because they can always interrupt cpu opera- tions. the most common use for such an interrupt is for serious system problems, such as program runaway or power failure. the xirq input is an updated version of the nonmaskable nmi input of earlier mcus. upon reset, both the x bit and i bits of the ccr are set to inhibit all maskable interrupts and xirq . after minimum system initialization, software can clear the x bit by a tap instruction, enabling xirq interrupts. thereafter, software cannot set the x bit. thus, an xirq interrupt is a nonmaskable interrupt. because the operation of the i-bit-relat- ed interrupt structure has no effect on the x bit, the internal xirq pin remains non- masked. in the interrupt priority logic, the xirq interrupt has a higher priority than any source that is maskable by the i bit. all i-bit-related interrupts operate normally with their own priority relationship. when an i-bit-related interrupt occurs, the i bit is automatically set by hardware after stacking the ccr byte. the x bit is not affected. when an x-bit-related interrupt oc- curs, both the x and i bits are automatically set by hardware after stacking the ccr. a return from interrupt instruction restores the x and i bits to their pre-interrupt request state. 5.4.3 illegal opcode trap because not all possible opcodes or opcode sequences are defined, the mcu in- cludes an illegal opcode detection circuit, which generates an interrupt request. when an illegal opcode is detected and the interrupt is recognized, the current value of the program counter is stacked. after interrupt service is complete, reinitialize the stack pointer so repeated execution of illegal opcodes does not cause stack underflow. left uninitialized, the illegal opcode vector can point to a memory location that contains an illegal opcode. this condition causes an infinite loop that causes stack underflow. the stack grows until the system crashes. the illegal opcode trap mechanism works for all unimplemented opcodes on all four opcode map pages. the address stacked as the return address for the illegal opcode interrupt is the address of the first byte of the illegal opcode. otherwise, it would be almost impossible to determine whether the illegal opcode had been one or two bytes. table 5-5 stacking order on entry to interrupts memory location cpu registers sp pcl sp C 1 pch sp C2 iyl sp C 3 iyh sp C 4 ixl sp C 5 ixh sp C 6 acca sp C 7 accb sp C 8 ccr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts technical data 5-11 the stacked return address can be used as a pointer to the illegal opcode so the illegal opcode service routine can evaluate the offending opcode. 5.4.4 software interrupt swi is an instruction, and thus cannot be interrupted until complete. swi is not inhib- ited by the global mask bits in the ccr. because execution of swi sets the i mask bit, once an swi interrupt begins, other interrupts are inhibited until swi is complete, or until user software clears the i bit in the ccr. 5.4.5 maskable interrupts the maskable interrupt structure of the mcu can be extended to include additional ex- ternal interrupt sources through the irq pin. the default configuration of this pin is a low-level sensitive wired-or network. when an event triggers an interrupt, a software accessible interrupt flag is set. when enabled, this flag causes a constant request for interrupt service. after the flag is cleared, the service request is released. 5.4.6 reset and interrupt processing figure 5-1 and figure 5-1 illustrate the reset and interrupt process. figure 5-1 illus- trates how the cpu begins from a reset and how interrupt detection relates to normal opcode fetches. figure 5-1 is an expansion of a block in figure 5-1 and illustrates in- terrupt priorities. figure 5-2 shows the resolution of interrupt sources within the sci subsystem. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts 5-12 technical data figure 5-1 processing flow out of reset (1 of 2) 2a bit x in y n xirq y n pin low? ccr = 1? begin instruction sequence 1a stack cpu registers set bits i and x fetch vector $fff4, $fff5 set bits s , i , and x reset mcu hardware power-on reset (por) external reset clock monitor fail (with cme = 1) cop watchdog timeout (with nocop = 0) delay 4064 e cycles load program counter with contents of $fffe, $ffff (vector fetch) load program counter with contents of $fffc, $fffd (vector fetch) load program counter with contents of $fffa, $fffb (vector fetch) highest priority lowest priority flow out of reset p1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts technical data 5-13 figure 5-1 processing flow out of reset (2 of 2) bit i in ccr = 1? 2a y n any i-bit interrupt y n pending? fetch opcode illegal opcode? y n wai y n instruction? swi instruction? y n rti instruction? y n execute this instruction stack cpu registers any n y interrupt pending? set bit i in ccr resolve interrupt priority and fetch vector for highest pending source stack cpu registers set bit i in ccr fetch vector $fff8, $fff9 stack cpu registers set bit i in ccr fetch vector $fff6, $fff7 restore cpu registers from stack 1a stack cpu registers see figure 5C2 flow out of reset p2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts 5-14 technical data figure 5-2 interrupt priority resolution (1 of 2) int priority res p1 2a begin set x bit in ccr fetch vector $fff4, fff5 x bit in ccr set ? yes no xirq pin low ? yes no highest priority interrupt ? yes no irq ? yes no fetch vector $fff2, fff3 fetch vector $fff0, fff1 rtii = 1 ? yes no real-time interrupt ? yes no fetch vector $ffee, ffef ic1i = 1 ? yes no timer ic1f ? yes no fetch vector $ffec, ffed ic2i = 1 ? yes no timer ic2f ? yes no fetch vector $ffea, ffeb ic3i = 1 ? yes no timer ic3f ? yes no fetch vector $ffe8, ffe9 oc1i = 1 ? yes no timer oc1f ? yes no 2b fetch vector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts technical data 5-15 figure 5-2 interrupt priority resolution (2 of 2) toi = 1? y n y n paovi = 1? paii = 1? y n spie = 1? y n y n flag y n y n flag flag y n flags y n paif = 1? spif = 1? or tof = 1? paovf = 1 fetch vector $ffde, $ffdf fetch vector $ffdc, $ffdd fetch vector $ffda, $ffdb fetch vector $ffd6, $ffd7 fetch vector $ffd8, $ffd9 oc2i = 1? y n y n oc3i = 1? oc4i = 1? y n oc5i = 1? y n flag y n y n flag flag y n flag y n oc4f = 1? oc5f = 1? oc2f = 1? oc3f = 1 fetch vector $ffe6, $ffe7 fetch vector $ffe4, $ffe5 fetch vector $ffe2, $ffe3 fetch vector $ffe0, $ffe1 modf = 1? interrupt? see figure 9C7 2a 2b end fetch vector $fff2, $fff3 sci int pri res p2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts 5-16 technical data figure 5-3 interrupt source resolution within sci 5.5 low-power operation both stop and wait suspend cpu operation until a reset or interrupt occurs. the wait condition suspends processing and reduces power consumption to an interme- diate level. the stop condition turns off all on-chip clocks and reduces power con- sumption to an absolute minimum while retaining the contents of all 192 bytes of ram. 5.5.1 wait the wai opcode places the mcu in the wait condition, during which the cpu regis- ters are stacked and cpu processing is suspended until a qualified interrupt is detect- ed. the interrupt can be an external irq , an xirq , or any of the internally generated interrupts, such as the timer or serial interrupts. the on-chip crystal oscillator remains active throughout the wait standby period. the reduction of power in the wait condition depends on how many internal clock sig- flag y n or = 1? y n y n tdre = 1? tc = 1? y n idle = 1? y n y n y n y n ilie = 1? rie = 1? tie = 1? begin re = 1? y n y n te = 1? tcie = 1? y n re = 1? y n rdrf = 1? valid sci request no valid sci request int source res f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts technical data 5-17 nals driving on-chip peripheral functions can be shut down. the cpu is always shut down during wait. while in the wait state, the address/data bus repeatedly runs read cycles to the address where the ccr contents were stacked. the mpu leaves the wait state when it senses any interrupt that has not been masked. the free-running timer system is shut down only if the i bit is set to one and the cop system is disabled by nocop being set to one. several other systems can also be in a reduced power consumption state depending on the state of software-controlled configuration control bits. the spi system is enabled or disabled by the spe control bit. the sci transmitter is enabled or disabled by the te bit, and the sci receiver is enabled or disabled by the re bit. therefore the power consumption in wait is de- pendent on the particular application. 5.5.2 stop executing the stop instruction while the s bit in the ccr is equal to zero places the mcu in the stop condition. if the s bit is not zero, the stop opcode is treated as a no-op (nop). the stop condition offers minimum power consumption because all clocks, including the crystal oscillator, are stopped while in this mode. to exit stop and resume normal processing, a logic low level must be applied to one of the external interrupts (irq or xirq ), or to the reset pin. a pending edge-triggered irq can also bring the cpu out of stop. because all clocks are stopped in this mode, all internal peripheral functions also stop. the data in the internal ram is retained as long as v dd power is maintained. the cpu state and i/o pin levels are static and are unchanged by stop. therefore, when an interrupt comes to restart the system, the mcu resumes processing as if there were no interruption. if reset is used to restart the system a normal reset sequence results where all i/o pins and functions are also restored to their initial states. to use the irq pin as a means of recovering from stop, the i bit in the ccr must be clear (irq not masked). the xirq pin can be used to wake up the mcu from stop regardless of the state of the x bit in the ccr, although the recovery sequence de- pends on the state of the x bit. if x is set to zero (xirq not masked), the mcu starts up, beginning with the stacking sequence leading to normal service of the xirq re- quest. if x is set to one (xirq masked or inhibited), then processing continues with the instruction that immediately follows the stop instruction, and no xirq interrupt service is requested or pending. because the oscillator is stopped in stop mode, a restart delay may be imposed to allow oscillator stabilization upon leaving stop. if the internal oscillator is being used, this delay is required; however, if a stable external oscillator is being used, the dly control bit can be used to bypass this startup delay. the dly control bit is set by reset and can be optionally cleared during initialization. if the dly equal to zero option is used to avoid startup delay on recovery from stop, then reset should not be used as the means of recovering from stop, as this causes dly to be set again by reset, im- posing the restart delay. this same delay also applies to power-on-reset, regardless of the state of the dly control bit, but does not apply to a reset while the clocks are running. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts 5-18 technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel i/o technical data 6-1 section 6 parallel i/o the MC68HC11d3 has four 8-bit i/o ports; a, b, c, and d. in single-chip and bootstrap modes, all ports are parallel i/o data ports. in expanded multiplexed and test modes, ports b and c, and lines data6/as and data7/r/w are a memory expansion bus with port b as the high order address bus, port c as the multiplexed address and data bus, as as the demultiplexing signal, and r/w as the data bus direction control. refer to table 6-1 , which is a summary of the ports and their shared functions: 6.1 port a port a bits handle the timer functions and can also be used as general-purpose i/o. in both the normal operating modes, port a can be configured for four timer input capture (ic) and three timer output compare (oc) functions, or four oc and three ic functions with either a pulse accumulator input (pai) or a fifth oc function. *this pin is not bonded in the 40-pin version. 6.2 port b in single-chip mode, all port b pins are general-purpose i/o (pb[7:0]). in expanded multiplexed mode, all port b pins act as high-order address bits (addr[15:8]). table 6-1 i/o ports port input pins output pins bidirectional pins shared functions port a 3 3 2 timer port b 8 high order address port c 8 low order address and data bus port d 8 sci, spi, as, and r/ porta port a data $0000 bit 7654321bit 0 pa7 pa6* pa5 pa4* pa3 pa2 pa1 pa0 reset: hiz 0 0 0 hiz hiz hiz hiz alt. func: pai oc2 oc3 oc4 ic4/oc5 ic1 ic2 ic3 and/or: oc1 oc1 oc1 oc1 oc1 portb port b data $0004 bit 7654321bit 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 s. chip or boot: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 reset: reset configures pins as hiz inputs expan. or test: addr15 addr14 addr13 addr12 addr11 addr10 addr9 addr8 reset: reset configures pins as high-order address outputs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel i/o 6-2 technical data ddb[7:0] data direction for port b 0 = corresponding port b pin configured for input only 1 = corresponding port b pin configured as output 6.3 port c port c pins are general-purpose i/o (pc[7:0]) in single-chip mode. in expanded mul- tiplexed mode, port c pins are configured as multiplexed address/data pins. during the data cycle, bits [7:0] (pc[7:0]) are bidirectional data pins controlled by the r/w signal. ddc[7:0] data direction for port c 0 = input 1 = output 6.4 port d the eight port d bits (pd[7:0]) can be used for general-purpose i/o, for the sci and spi subsystems, or for bus data direction control. port d can be read at any time. in- puts return the sensed levels at the pin; outputs return the input level of the port d pin drivers. if port d is written, the data is stored in an internal latch, and can be driven only if port d is configured for general-purpose output. this port shares functions with the on-chip sci and spi subsystems, while bits 6 and 7 control the direction of data flow on the bus in expanded and special test modes. ddrb data direction register for port b $0006 bit 7654321bit 0 ddb7 ddb6 ddb5 ddc4 ddb3 ddb2 ddb1 ddb0 reset:00000000 portc port c data $0003 bit 7654321bit 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 s. chip or boot: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: reset configures pins as hiz inputs expan. or test: addr7/ data7 addr6/ data6 addr5/ data5 addr4/ data4 addr3/ data3 addr2/ data2 addr1/ data1 addr0/ data0 reset: reset configures pins as multiplexed, low-order address/data i/o ddrc data direction register for port c $0007 bit 7654321bit 0 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel i/o technical data 6-3 ddd[7:0] data direction for port d when port d is a general-purpose i/o port, the ddrd register controls the direction of the i/o pins as follows: 0 = configures the corresponding port d pin for input 1 = configures the corresponding port d pin for output in expanded and test modes, bits 6 and 7 are dedicated as and r/w outputs. when port d is functioning with the spi system enabled, bit 5 is dedicated as the slave select (ss ) input. in spi slave mode, ddd5 has no meaning or effect. in spi master mode, ddd5 affects port d bit 5 as follows: 0 = port d bit 5 is an error-detect input to the spi. 1 = port d bit 5 is configured as a general-purpose output line. if the spi is enabled and expects port d bits 2, 3, and 4 (miso, mosi, and sck) to be inputs, then they are inputs, regardless of the state of ddrd bits 2, 3, and 4. if the spi expects port d bits 2, 3, and 4 to be outputs, they are outputs only if ddrd bits 2, 3, and 4 are set. ddra7 data direction control for port a bit 7 refer to section 9 timing system . paen pulse accumulator system enable refer to section 9 timing system . pamod pulse accumulator mode refer to section 9 timing system . pedge pulse accumulator edge control refer to section 9 timing system . ddra3 data direction for port a bit 3 overridden if an output compare function is configured to control the pa3 pin. 0 = input only 1 = output portd port d data $0008 bit 7654321bit 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 reset:00000000 alt. func.: r/w as sck mosi miso txd rxd ddrd data direction register for port d $0009 bit 7654321bit 0 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 reset:00000000 pactl pulse accumulator control $0026 bit 7654321bit 0 ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel i/o 6-4 technical data i4/o5 configure ti4/o5 register for ic4 or oc5 0 = oc5 function enabled 1 = ic4 function enabled rtr[1:0] real-time interrupt (rti) rate refer to section 9 timing system . 6.5 parallel i/o control register (pioc) pioc configures and controls handshake i/o functions in mcus where this function is available. in the MC68HC11d3, however, only the cwom bit in the pioc register is usable. the cwom bit is cleared so that port c is not in wired-or mode. cwom port c wired-or mode (affects all eight port c pins) 0 = port c outputs are normal cmos outputs 1 = port c outputs are open-drain outputs pioc parallel i/o control $0002 bit 7654321bit 0 00cwom00000 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data 7-1 section 7 serial communications interface the serial communications interface (sci) is a universal asynchronous receiver trans- mitter (uart), one of two independent serial i/o subsystems in the MC68HC11d3. it has a standard nonreturn to zero (nrz) format (one start, eight or nine data, and one stop bit). several baud rates are available. the sci transmitter and receiver are inde- pendent, but use the same data format and bit rate. 7.1 data format the serial data format requires the following conditions: 1. an idle line in the high state before transmission or reception of a message 2. a start bit, logic zero, transmitted or received, that indicates the start of each character 3. data that is transmitted and received least significant bit (lsb) first 4. a stop bit, logic one, used to indicate the end of a frame (a frame consists of a start bit, a character of eight or nine data bits, and a stop bit.) 5. a break (defined as the transmission or reception of a logic zero for some mul- tiple number of frames). selection of the word length is controlled by the m bit of sci control register sccr1. 7.2 transmit operation the sci transmitter includes a parallel transmit data register (scdr) and a serial shift register. the contents of the serial shift register can only be written through the scdr. this double buffered operation allows a character to be shifted out serially while an- other character is waiting in the scdr to be transferred into the serial shift register. the output of the serial shift register is applied to txd as long as transmission is in progress or the transmit enable (te) bit of serial communication control register 2 (sccr2) is set. the block diagram, figure 7-1 , shows the transmit serial shift register, and the buffer logic at the top of the figure. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface 7-2 technical data figure 7-1 sci transmitter block diagram 7.3 receive operation during receive operations, the transmit sequence is reversed. the serial shift register receives data and transfers it to a parallel receive data register (scdr) as a complete word. refer to figure 7-2 . this double buffered operation allows a character to be shifted in serially while another character is already in the scdr. an advanced data 11 sci tx block fe nf or idle rdrf tc tdre scsr interrupt status sbk rwu re te ilie rie tcie tie sccr2 sci control 2 transmitter control logic tcie tc tie tdre sci rx requests sci interrupt request internal data bus pin buffer and control h(8)76543210l 10 (11) - bit tx shift register ddd1 pd1 txd scdr tx buffer transfer tx buffer shift enable jam enable preamblejam 1s breakjam 0s (write only) force pin direction (out) size 8/9 wake m t8 r8 sccr1 sci control 1 transmitter baud rate clock 8 8 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data 7-3 recovery scheme distinguishes valid data from noise in the serial data stream. the data input is selectively sampled to detect receive data, and a majority voting circuit determines the value and integrity of each bit. figure 7-2 sci receiver block diagram 11 sci rx block fe nf or idle rdrf tc tdre scsr sci status 1 sbk rwu re te ilie rie tcie tie sccr2 sci control 2 wake m t8 r8 wakeup logic rie or ilie idle sci tx requests sci interrupt request internal data bus pin buffer and control ddd0 pd0 rxd scdr rx buffer stop (8)76543210 10 (11) - bit rx shift register (read only) sccr1 sci control 1 rie rdrf start msb all ones data recovery 16 rwu re m disable driver receiver baud rate clock 8 8 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface 7-4 technical data 7.4 wake-up feature the wake-up feature reduces sci service overhead in multiple receiver systems. soft- ware for each receiver evaluates the first character of each message. the receiver is placed in wakeup mode by writing a one to the rwu bit in the sccr2 register. while rwu is one, all of the receiver-related status flags (rdrf, idle, or, nf, and fe) are inhibited (cannot become set). although rwu can be cleared by a software write to sccr2, to do so would be unusual. normally rwu is set by software and is cleared automatically with hardware. whenever a new message begins, logic alerts the sleep- ing receivers to wake up and evaluate the initial character of the new message. two methods of wake-up are available: idle line wake-up and address mark wake-up. during idle line wake-up, a sleeping receiver awakens as soon as the rxd line be- comes idle. in the address mark wake-up, logic one in the most significant bit (msb) of a character wakes up all sleeping receivers. 7.4.1 idle-line wakeup to use the receiver wake-up method, establish a software addressing scheme to allow the transmitting devices to direct a message to individual receivers or to groups of re- ceivers. this addressing scheme can take any form as long as all transmitting and re- ceiving devices are programmed to understand the same scheme. because the addressing information is usually the first frame(s) in a message, receivers that are not part of the current task do not become burdened with the entire set of addressing frames. all receivers are awake (rwu = 0) when each message begins. as soon as a receiver determines that the message is not intended for it, software sets the rwu bit (rwu = 1), which inhibits further flag setting until the rxd line goes idle at the end of the message. as soon as an idle line is detected by receiver logic, hardware auto- matically clears the rwu bit so that the first frame of the next message can be re- ceived. this type of receiver wakeup requires a minimum of one idle-line frame time between messages, and no idle time between frames in a message. 7.4.2 address-mark wakeup the serial characters in this type of wakeup consist of seven (eight if m = 1) information bits and an msb, which indicates an address character (when set to one mark). the first character of each message is an addressing character (msb = 1). all receivers in the system evaluate this character to determine if the remainder of the message is di- rected toward this particular receiver. as soon as a receiver determines that a mes- sage is not intended for it, the receiver activates the rwu function by using a software write to set the rwu bit. because setting rwu inhibits receiver-related flags, there is no further software overhead for the rest of this message. when the next message be- gins, its first character has its msb set, which automatically clears the rwu bit and enables normal character reception. the first character whose msb is set is also the first character to be received after wakeup because rwu gets cleared before the stop bit for that frame is serially received. this type of wakeup allows messages to include gaps of idle time, unlike the idle-line method, but there is a loss of efficiency because of the extra bit time for each character (address bit) required for all characters. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data 7-5 7.5 sci error detection three error conditions, scdr overrun, received bit noise, and framing can occur dur- ing generation of sci system interrupts. three bits (or, nf, and fe) in the serial com- munications status register (scsr) indicate if one of these error conditions exists. the overrun error (or) bit is set when the next byte is ready to be transferred from the re- ceive shift register to the scdr and the scdr is already full (rdrf bit is set). when an overrun error occurs, the data that caused the overrun is lost and the data that was already in scdr is not disturbed. the or is cleared when the scsr is read (with or set), followed by a read of the scdr. the noise flag (nf) bit is set if there is noise on any of the received bits, including the start and stop bits. the nf bit is not set until the rdrf flag is set. the nf bit is cleared when the scsr is read (with fe equal to one) followed by a read of the scdr. when no stop bit is detected in the received data character, the framing error (fe) bit is set. fe is set at the same time as the rdrf. if the byte received causes both fram- ing and overrun errors, the processor only recognizes the overrun error. the framing error flag inhibits further transfer of data into the scdr until it is cleared. the fe bit is cleared when the scsr is read (with fe equal to one) followed by a read of the scdr. 7.6 sci registers there are five addressable registers in the sci. 7.6.1 serial communications data register (scdr) scdr is a parallel register that performs two functions. it is the receive data register when it is read, and the transmit data register when it is written. reads access the re- ceive data buffer and writes access the transmit data buffer. receive and transmit are double buffered. *u = unaffected 7.6.2 serial communications control register 1 (sccr1) the sccr1 register provides the control bits that determine word length and select the method used for the wake-up feature. r8 receive data bit 8 if m bit is set, r8 stores the ninth bit in the receive data character. scdr sci data register $002f bit 7654321bit 0 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 reset:u*uuuuuuu sccr1 sci control register 1 $002c bit 7654321bit 0 r8 t8 0 m wake 0 0 0 reset:uu000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface 7-6 technical data t8 transmit data bit 8 if m bit is set, t8 stores ninth bit in transmit data character. m mode (select character format) 0 = start bit, 8 data bits, 1 stop bit 1 = start bit, 9 data bits, 1 stop bit wake wake-up by address mark/idle 0 = wake-up by idle line recognition 1 = wake-up by address mark (most significant data bit set) 7.6.3 serial communications control register 2 (sccr2) the sccr2 register provides the control bits that enable or disable individual sci functions. tie transmit interrupt enable 0 = tdre interrupts disabled 1 = sci interrupt requested when tdre status flag is set tcie transmit complete interrupt enable 0 = tc interrupts disabled 1 = sci interrupt requested when tc status flag is set rie receiver interrupt enable 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when rdrf flag or the or status flag is set ilie idle line interrupt enable 0 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te transmitter enable when te goes from zero to one, one unit of idle character time (logic one) is queued as a preamble. 0 = transmitter disabled 1 = transmitter enabled re receiver enable 0 = receiver disabled 1 = receiver enabled rwu receiver wake-up control 0 = normal sci receiver 1 = wake-up enabled and receiver interrupts inhibited sccr2 sci control register 2 $002d bit 7654321bit 0 tie tcie rie ilie te re rwu sbk reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data 7-7 sbk send break at least one character time of break is queued and sent each time sbk is written to one. more than one break may be sent if the transmitter is idle at the time the sbk bit is toggled on and off, as the baud rate clock edge could occur between writing the one and writing the zero to sbk. 0 = break generator off 1 = break codes generated as long as sbk = 1 7.6.4 serial communication status register (scsr) the scsr provides inputs to the interrupt logic circuits for generation of the sci sys- tem interrupt. tdre transmit data register empty flag this flag is set when scdr is empty. clear the tdre flag by reading scsr with tdre set and then writing to scdr. 0 = scdr busy 1 = scdr empty tc transmit complete flag this flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). clear the tc flag by reading scsr with tc set and then writing to scdr. 0 = transmitter busy 1 = transmitter idle rdrf receive data register full flag this flag is set if a received character is ready to be read from scdr. clear the rdrf flag by reading scsr with rdrf set and then reading scdr. 0 = scdr empty 1 = scdr full idle idle line detected flag this flag is set if the rxd line is idle. once cleared, idle is not set again until the rxd line has been active and becomes idle again. the idle flag is inhibited when rwu = 1. clear idle by reading scsr with idle set and then reading scdr. 0 = rxd line is active 1 = rxd line is idle or overrun error flag or is set if a new character is received before a previously received character is read from scdr. clear the or flag by reading scsr with or set and then reading scdr. 0 = no overrun 1 = overrun detected scsr sci status register $002e bit 7654321bit 0 tdre tc rdrf idle or nf fe 0 reset:11000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface 7-8 technical data nf noise error flag nf is set if majority sample logic detects anything other than a unanimous decision. clear nf by reading scsr with nf set and then reading scdr. 0 = unanimous decision 1 = noise detected fe framing error fe is set when a 0 is detected where a stop bit was expected. clear the fe flag by reading scsr with fe set and then reading scdr. 0 = stop bit detected 1 = 0 detected 7.6.5 baud rate register (baud) use this register to select different baud rates for the sci system. the scp[1:0] bits function as a prescaler for the scr[2:0] bits. together, these five bits provide multiple baud rate combinations for a given crystal frequency. normally, this register is written once during initialization. the prescaler is set to its fastest rate by default out of reset, and can be changed at any time. refer to table 7-1 and table 7-2 for normal baud rate selections. tclr clear baud rate counters (test) rckb sci baud rate clock check (test) scp1, scp0 sci baud rate prescaler selects these two bits select a prescale factor for the sci baud rate generator that determines the highest possible baud rate. scr[2:0] sci baud rate selects these three bits select receiver and transmitter bit rate based on output from baud rate prescaler stage. baud baud rate $002b bit 7654321bit 0 tclr 0 scp1 scp0 rckb scr2 scr1 scr0 reset:00000uuu table 7-1 baud rate prescale selects scp[1:0] divide crystal frequency in mhz internal clock by 4.0 mhz (baud) 8.0 mhz (baud) 10.0 mhz (baud) 12.0 mhz (baud) 0 0 1 62.50 k 125.0 k 156.25 k 187.5 k 0 1 3 20.83 k 41.67 k 52.08 k 62.5 k 1 0 4 15.625 k 31.25 k 38.4 k 46.88 k 1 1 13 4800 9600 12.02 k 14.42 k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data 7-9 the prescale bits, scp[1:0], determine the highest baud rate and the scr[2:0] bits se- lect an additional binary submultiple ( 3 1 , 3 2, 3 4 , through 3 128) of this highest baud rate. the result of these two dividers in series is the 16 x receiver baud rate clock. the scr[2:0] bits are not affected by reset and can be changed at any time, although they should not be changed when any sci transfer is in progress. figure 7-3 illustrates the sci baud rate timing chain. the prescale select bits deter- mine the highest baud rate. the rate select bits determine additional divide by two stages to arrive at the receiver timing (rt) clock rate. the baud rate clock is the result of dividing the rt clock by 16. table 7-2 baud rate selects scr[2:0] divide prescaler highest baud rate (prescaler output from previous table) by 4800 9600 38.4 k 0 0 0 1 4800 9600 38.4 k 0 0 1 2 2400 4800 19.2 k 0 1 0 4 1200 2400 9600 0 1 1 8 600 1200 4800 1 0 0 16 300 600 2400 1 0 1 32 150 300 1200 1 1 0 64 150 600 1 1 1 128 300 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface 7-10 technical data figure 7-3 sci baud rate diagram 7.7 status flags and interrupts the sci transmitter has two status flags. these status flags can be read by software (polled) to tell when the corresponding condition exists. alternatively, a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests when the corresponding condition is present. status flags are automatically set by hardware logic conditions, but must be cleared by software, which provides an interlock mechanism that enables logic to know when software has noticed the status indication. the software clearing sequence for these flags is automatic functions that are normally performed in response to the status flags also satisfy the conditions of the clearing sequence. sci baud generator 3 4 13 oscillator and clock generator ( 4) xtal extal e as internal bus clock (ph2) 1:1 scp[1:0] 1:0 0:1 0:0 2 0:0:0 2 0:0:1 2 0:1:0 2 0:1:1 2 1:0:0 2 1:0:1 2 1:1:0 1:1:1 16 sci receive baud rate (16x) scr[2:0] sci transmit baud rate (1x) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data 7-11 tdre and tc flags are normally set when the transmitter is first enabled (te set to one). the tdre flag indicates there is room in the transmit queue to store another data character in the tdr. the tie bit is the local interrupt mask for tdre. when tie is zero, tdre must be polled. when tie and tdre are one, an interrupt is requested. the tc flag indicates the transmitter has completed the queue. the tcie bit is the lo- cal interrupt mask for tc. when tcie is zero, tc must be polled; when tcie is one and tc is one, an interrupt is requested. writing a zero to te requests that the transmitter stop when it can. the transmitter completes any transmission in progress before actually shutting down. only an mcu reset can cause the transmitter to stop and shut down immediately. if te is written to zero when the transmitter is already idle, the pin reverts to its general-purpose i/o function (synchronized to the bit-rate clock). if anything is being transmitted when te is written to zero, that character is completed before the pin reverts to general-purpose i/o, but any other characters waiting in the transmit queue are lost. the tc and tdre flags are set at the completion of this last character, even though te has been dis- abled. the sci receiver has five status flags, three of which can generate interrupt requests. the status flags are set by the sci logic in response to specific conditions in the re- ceiver. these flags can be read (polled) at any time by software. refer to figure 7-4 , which shows sci interrupt arbitration. when an overrun takes place, the new character is lost, and the character that was in its way in the parallel rdr is undisturbed. rdrf is set when a character has been received and transferred into the parallel rdr. the or flag is set instead of rdrf if overrun occurs. a new character is ready to be transferred into rdr before a previous character is read from rdr. the nf and fe flags provide additional information about the character in the rdr, but do not generate interrupt requests. the last receiver status flag and interrupt source come from the idle flag. the rxd line is idle if it has constantly been at logic one for a full character time. the idle flag is set only after the rxd line has been busy and becomes idle, which prevents repeat- ed interrupts for the whole time rxd remains idle. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface 7-12 technical data figure 7-4 interrupt source resolution within sci flag y n or = 1? y n y n tdre = 1? tc = 1? y n idle = 1? y n y n y n y n ilie = 1? rie = 1? tie = 1? begin re = 1? y n y n te = 1? tcie = 1? y n re = 1? y n rdrf = 1? valid sci request no valid sci request int source res f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface technical data 8-1 section 8 serial peripheral interface the serial peripheral interface (spi), an independent serial communications sub- system, allows the mcu to communicate synchronously with peripheral devices, such as transistor-transistor logic (ttl) shift registers, liquid crystal diode (lcd) display drivers, analog-to-digital converter subsystems, and other microprocessors. the spi is also capable of inter-processor communication in a multiple master system. the spi system can be configured as either a master or a slave device with data rates as high as one half of the e-clock rate when configured as master, and as fast as the e-clock rate when configured as slave. 8.1 functional description the central element in the spi system is the block containing the shift register and the read data buffer. the system is single buffered in the transmit direction and double buffered in the receive direction. this means that new data for transmission cannot be written to the shifter until the previous transfer is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second se- rial character. as long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition occurs. a sin- gle mcu register address is used for reading data from the read data buffer, and for writing data to the shifter. the spi status block represents the spi status functions (transfer complete, write col- lision, and mode fault) performed by the serial peripheral status register (spsr). the spi control block represents those functions that control the spi system through the serial peripheral control register (spcr). refer to figure 8-1 , which shows the spi block diagram. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface 8-2 technical data figure 8-1 spi block diagram 8.2 spi transfer formats during an spi transfer, data is simultaneously transmitted and received. a serial clock line synchronizes shifting and sampling of the information on the two serial data lines. a slave select line allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the select line can optionally be used to indicate a multiple master bus contention. refer to figure 8-2 . 11 spi block spr0 spr1 cpha cpol mstr dwom spe spie spi control register modf wcol spif spi status register 8/16-bit shift register read data buffer msb lsb internal data bus spi interrupt request mstr spe mstr dwom spe spr0 spi clock (master) spi control select divider internal mcu clock clock logic clock pin control logic s m s m m s miso pd2 mosi pd3 sck pd4 ss pd5 spr1 2 4 16 32 8 8 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface technical data 8-3 figure 8-2 spi transfer format 8.2.1 clock phase and polarity controls software can select one of four combinations of serial clock phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or active low clock, and has no significant ef- fect on the transfer format. the clock phase (cpha) control bit selects one of two dif- ferent transfer formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polar- ity are changed between transfers to allow a master device to communicate with pe- ripheral slaves having different requirements. when cpha equals zero, the slave select (ss ) line must be negated and reasserted between each successive serial byte. also, if the slave writes data to the spi data reg- ister (spdr) while ss is active low, a write collision error results. when cpha equals one, the ss line can remain low between successive transfers. 8.3 spi signals the following paragraphs contain descriptions of the four spi signals: master in slave out (miso), master out slave in (mosi), serial clock (sck), and ss . spi transfer format 1 2345678 1 sck (cpol = 1) sck (cpol = 0) sck cycle # ss (to slave) 654321 lsb msb msb654321lsb 1 2 3 5 4 slave cpha=1 transfer in progress master transfer in progress slave cpha=0 transfer in progress 1. ss asserted 2. master writes to spdr 3. first sck edge 4. spif set 5. ss negated sample input data out (cpha = 0) sample input data out (cpha = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface 8-4 technical data 8.3.1 master in slave out miso is one of two unidirectional serial data signals. it is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high impedance state if the slave device is not selected. 8.3.2 master out slave in the mosi line is the second of the two unidirectional serial data signals. it is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge that the slave device uses to latch the data. 8.3.3 serial clock sck, an input to a slave device, is generated by the master device and synchronizes data movement in and out of the device through the mosi and miso lines. master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. there are four possible timing relationships that can be chosen by using control bits cpol and cpha in the serial peripheral control register (spcr). both master and slave devices must operate with the same timing. the spi clock rate select bits, spr[1:0], in the spcr of the master device, select the clock rate. in a slave device, spr[1:0] have no effect on the operation of the spi. 8.3.4 slave select the ss input of a slave device must be externally asserted before a master device can exchange data with the slave device. must be low before data transactions and must stay low for the duration of the transaction. the ss line of the master must be held high. if it goes low, a mode fault error flag (modf) is set in the serial peripheral status register (spsr). to disable the mode fault circuit, write a one in bit 5 of the port d data direction register. this sets the ss pin to act as a general-purpose output. the other three lines are dedicated to the spi when- ever the serial peripheral interface is on. the state of the master and slave cpha bits affects the operation of ss . cpha set- tings should be identical for master and slave. when cpha = 0, the shift clock is the or of ss with sck. in this clock phase mode, ss must go high between successive characters in an spi message. when cpha = 1, ss can be left low between succes- sive spi characters. in cases where there is only one spi slave mcu, its ss line can be tied to v ss as long as only cpha = 1 clock mode is used. 8.4 spi system errors two system errors can be detected by the spi system. the first type of error arises in a multiple-master system when more than one spi device simultaneously tries to be a master. this error is called a mode fault. the second type of error, write collision, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface technical data 8-5 indicates that an attempt was made to write data to the spdr while a transfer was in progress. when the spi system is configured as a master and the ss input line goes to active low, a mode fault error has occurred usually because two devices have attempted to act as master at the same time. in cases where more than one device is concurrent- ly configured as a master, there is a chance of contention between two pin drivers. for push-pull cmos drivers, this contention can cause permanent damage. the mode fault attempts to protect the device by disabling the drivers. the mstr control bit in the spcr and all four ddrd control bits associated with the spi are cleared. an in- terrupt is generated subject to masking by the spie control bit and the i bit in the ccr. other precautions may need to be taken to prevent driver damage. if two devices are made masters at the same time, mode fault does not help protect either one unless one of them selects the other as slave. the amount of damage possible depends on the length of time both devices attempt to act as master. a write collision error occurs if the spdr is written while a transfer is in progress. be- cause the spdr is not double buffered in the transmit direction, writes to spdr cause data to be written directly into the spi shift register. because this write corrupts any transfer in progress, a write collision error is generated. the transfer continues undis- turbed, and the write data that caused the error is not written to the shifter. a write collision is normally a slave error because a slave has no control over when a master initiates a transfer. a master knows when a transfer is in progress, so there is no reason for a master to generate a write-collision error, although the spi logic can detect write collisions in both master and slave devices. the spi configuration determines the characteristics of a transfer in progress. for a master, a transfer begins when data is written to spdr and ends when spif is set. for a slave with cpha equal to zero, a transfer starts when ss goes low and ends when ss returns high. in this case, spif is set at the middle of the eighth sck cycle when data is transferred from the shifter to the parallel data register, but the transfer is still in progress until ss goes high. for a slave with cpha equal to one, transfer be- gins when the sck line goes to its active level, which is the edge at the beginning of the first sck cycle. the transfer ends in a slave in which cpha equals one when spif is set. for a slave, after a byte transfer, sck must be in inactive state for at least 2 e- clock cycles before the next byte transfer begins. 8.5 spi registers the three spi registers, spcr, spsr, and spdr, provide control, status, and data storage functions. refer to the following information for a description of how these reg- isters are organized. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface 8-6 technical data 8.5.1 serial peripheral control spie serial peripheral interrupt enable 0 = spi interrupt disabled 1 = spi interrupt enabled spe serial peripheral system enable 0 = spi off 1 = spi on dwom port d wired-or mode dwom affects all six port d pins. 0 = normal cmos outputs 1 = open-drain outputs mstr master mode select 0 = slave mode 1 = master mode cpol clock polarity when the clock polarity bit is cleared and data is not being transferred, the sck pin of the master device has a steady state low value. when cpol is set, sck idles high. refer to figure 8-2 and 8.2.1 clock phase and polarity controls . cpha clock phase the clock phase bit, in conjunction with the cpol bit, controls the clock-data relation- ship between master and slave. the cpha bit selects one of two different clocking protocols. refer to figure 8-2 and 8.2.1 clock phase and polarity controls . spr1 and spr0 spi clock rate selects these two serial peripheral rate bits select one of four baud rates to be used as sck if the device is a master; however, they have no effect in the slave mode. spcr serial peripheral control register $0028 bit 7654321bit 0 spie spe dwom mstr cpol cpha spr1 spr0 reset:000001uu spr[1:0] e clock divide by frequency at e = 2 mhz (baud) 0 0 2 1.0 mhz 0 1 4 500 khz 1 0 16 125 khz 1 1 32 62.5 khz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface technical data 8-7 8.5.2 serial peripheral status spif spi transfer complete flag spif is set upon completion of data transfer between the processor and the external device. if spif goes high, and if spie is set, a serial peripheral interrupt is generated. to clear the spif bit, read the spsr with spif set, then access the spdr. unless spsr is read (with spif set) first, attempts to write spdr are inhibited. wcol write collision clearing the wcol bit is accomplished by reading the spsr (with wcol set) fol- lowed by an access of spdr. refer to 8.3.4 slave select and 8.4 spi system errors . 0 = no write collision 1 = write collision bit 5 not implemented always reads zero modf mode fault to clear the modf bit, read the spsr (with modf set), then write to the spcr. refer to 8.3.4 slave select and 8.4 spi system errors . 0 = no mode fault 1 = mode fault bits [3:0] not implemented always read zero 8.5.3 serial peripheral data i/o the spdr is used when transmitting or receiving data on the serial bus. only a write to this register initiates transmission or reception of a byte, and this only occurs in the master device. at the completion of transferring a byte of data, the spif status bit is set in both the master and slave devices. a read of the spdr is actually a read of a buffer. to prevent an overrun and the loss of the byte that caused the overrun, the first spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated. note spi is double buffered in and single buffered out. spsr serial peripheral status register $0029 bit 7654321bit 0 spifwcol0modf0000 reset:00000000 spdr spi data register $002a bit 7654321bit 0 bit 7654321bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface 8-8 technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system technical data 9-1 section 9 timing system the m68hc11 timing system is composed of five clock divider chains. the main clock divider chain includes a 16-bit free-running counter, which is driven by a programma- ble prescaler. the main timer's programmable prescaler provides one of the four clocking rates to drive the 16-bit counter. two prescaler control bits select the prescale rate. the prescaler output divides the system clock by 1, 4, 8, or 16. taps off of this main clocking chain drive circuitry that generates the slower clocks used by the pulse accu- mulator, the real-time interrupt (rti), and the computer operating properly (cop) watchdog subsystems, also described in this section. refer to figure 9-1 . all main timer system activities are referenced to this free-running counter. the counter begins incrementing from $0000 as the mcu comes out of reset, and contin- ues to the maximum count, $ffff. at the maximum count, the counter rolls over to $0000, sets an overflow flag, and continues to increment. as long as the mcu is run- ning in a normal operating mode, there is no way to reset, change, or interrupt the counting. the capture/compare subsystem features three input capture channels, four output compare channels, and one channel that can be selected to perform either in- put capture or output compare. each of the three input capture functions has its own 16-bit input capture register (time capture latch) and each of the output compare func- tions has its own 16-bit compare register. all timer functions, including the timer over- flow and rti have their own interrupt controls and separate interrupt vectors. the pulse accumulator contains an 8-bit counter and edge select logic. the pulse ac- cumulator can operate in either event counting or gated time accumulation modes. during event counting mode, the pulse accumulator's 8-bit counter increments when a specified edge is detected on an input signal. during gated time accumulation mode, an internal clock source increments the 8-bit counter while an input signal has a pre- determined logic level. rti is a programmable periodic interrupt circuit that permits pacing the execution of software routines by selecting one of four interrupt rates. the cop watchdog clock input (e ? 2 15 ) is tapped off of the free-running counter chain. the cop automatically times out unless it is serviced within a specific time by a pro- gram reset sequence. if the cop is allowed to time out, a reset is generated, which drives the reset pin low to reset the mcu and the external system. refer to table 9-1 for crystal related frequencies and periods. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system 9-2 technical data figure 9-1 timer clock divider chains timer div chain oscillator and clock generator as e clock spi sci receiver clock sci transmit clock e2 6 pulse accumulator tcnt tof real-time interrupt e2 13 4 e2 15 rq q s r q q s force cop reset system reset clear cop timer ff2 ff1 (divide by four) internal bus clock (ph2) ic/oc 16 cr[1:0] prescaler (1, 4, 16, 64) prescaler ( 2, 4, 16, 32) spr[1:0] prescaler ( 1, 3, 4, 13) scp[1:0] prescaler ( 1, 2, 4, 8) rtr[1:0] prescaler ( 1, 2, 4,....128) scr[2:0] prescaler ( 1, 4, 8, 16) pr[1:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system technical data 9-3 9.1 timer structure figure 9-1 shows the capture/compare system block diagram. the port a pin control block includes logic for timer functions and for general-purpose i/o. for pins pa2, pa1, and pa0, this block contains both the edge-detection logic and the control logic that enables the selection of which edge triggers an input capture. the digital level on pa[2:0] can be read at any time (read porta register), even if the pin is being used for the input capture function. pins pa[6:4] are used for either general-purpose output, or as output compare pins. pin pa3 can be used for general-purpose i/o, input capture 4, output compare 5, or output compare 1. when one of these pins is being used for an output compare function, it cannot be written directly as if it were a general-purpose output. each of the output compare functions (oc5Coc2) is related to one of the port a output pins. output compare one (oc1) has extra control logic, allowing it optional control of any combination of the pa[7:3] pins. the pa7 pin can be used as a general- purpose i/o pin, as an input to the pulse accumulator, or as an oc1 output pin. table 9-1 timer summary xtal frequencies 4.0 mhz 8.0 mhz 12.0 mhz other rates control 1.0 mhz 2.0 mhz 3.0 mhz (e) bits 1000 ns 500 ns 333 ns (1/e) pr[1:0] main timer count rates 0 0 1 count overflow 1.0 s 65.536 ms 500 ns 32.768 ms 333 ns 21.845 ms (e/1) (e/2 16 ) 0 1 1 count overflow 4.0 s 262.14 ms 2.0 s 131.07 ms 1.333 s 87.381 ms (e/4) (e/2 18 ) 1 0 1 count overflow 8.0 s 524.29 ms 4.0 s 262.14 ms 2.667 s 174.76 ms (e/8) (e/2 19 ) 1 1 1 count overflow 16.0 s 1.049 s 8.0 s 524.29 ms 5.333 s 349.52 ms (e/16) (e/2 20 ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system 9-4 technical data figure 9-2 capture/compare block diagram 9.2 input capture the input capture function records the time an external event occurs by latching the value of the free-running counter when a selected edge is detected at the associated timer input pin. software can store latched values and use them to compute the peri- odicity and duration of events. for example, by storing the times of successive edges of an incoming signal, software can determine the period and pulse width of a signal. to measure period, two successive edges of the same polarity are captured. to mea- sure pulse width, two alternate polarity edges are captured. 11 cc block system 16-bit latch clk 4 5 6 7 8 bit 7 bit 6 bit 5 bit 4 bit 3 parallel port pin control oc1i oc2i oc3i oc4i i4/o5i tflg 1 status flags foc1 foc2 foc3 foc4 foc5 oc1f oc2f oc3f oc4f i4/o5f pa3 pa4 pa5 pa6 pa7 i4/o5 16-bit comparator = toc1 (hi) toc1 (lo) 16-bit comparator = toc2 (hi) toc2 (lo) 16-bit comparator = toc3 (hi) toc3 (lo) 16-bit comparator = toc4 (hi) toc4 (lo) 16-bit comparator = ti4/o5 (hi) ti4/o5 (lo) 16-bit free running counter tcnt (hi) tcnt (lo) 9 toi tof interrupt requests prescaler divide by 1, 4, 8, 16 pr1 16-bit timer bus oc5 ic4 tmsk 1 interrupt enables cforc force output pin functions pa0 3 2 1 bit 2 bit 1 bit 3 ic1i ic2i ic3i ic1f ic2f ic3f pa1 pa2 16-bit latch tic1 (hi) tic1 (lo) clk 16-bit latch tic2 (hi) tic2 (lo) clk 16-bit latch tic3 (hi) tic3 (lo) clk ic3 ic2 ic1 pr0 clock oc1 oc2/oc1 oc3/oc1 oc4/oc1 ic4/oc5 oc1 compare tmsk 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system technical data 9-5 in most cases, input capture edges are asynchronous to the internal timer counter, which is clocked relative to the ph2 clock. these asynchronous capture requests are synchronized to ph2 so that the latching occurs on the opposite half cycle of ph2 from when the timer counter is being incremented. this synchronization process introduces a delay from when the edge occurs to when the counter value is detected. because these delays offset each other when the time between two edges is being measured, the delay can be ignored. when an input capture is being used with an output com- pare, there is a similar delay between the actual compare point and when the output pin changes state. the control and status bits that implement the input capture functions are contained in the pactl, tctl2, tmsk1, and tflg1 registers. to configure port a bit 3 as an input capture, clear the ddra3 bit of the pactl reg- ister. note that this bit is cleared out of reset. to enable pa3 as the fourth input cap- ture, set the i4/o5 bit in the pactl register. otherwise, pa3 is configured as a fifth output compare out of reset, with bit i4/o5 being cleared. if the ddra3 bit is set (con- figuring pa3 as an output), and ic4 is enabled, then writes to pa3 cause edges on the pin to result in input captures. writing to ti4/o5 has no effect when the ti4/o5 register is acting as ic4. 9.2.1 timer control 2 register use the control bits of this register to program input capture functions to detect a par- ticular edge polarity on the corresponding timer input pin. each of the input capture functions can be independently configured to detect rising edges only, falling edges only, any edge (rising or falling), or to disable the input capture function. the input cap- ture functions operate independently of each other and can capture the same tcnt value if the input edges are detected within the same timer count cycle. edgxb and edgxa input capture edge control there are four pairs of these bits. each pair is cleared to zero by reset and must be encoded to configure the corresponding input capture edge detector circuit. ic4 func- tions only if the i4/o5 bit in the pactl register is set. refer to table 9-2 for timer con- trol configuration. tctl2 timer control 2 $0021 bit 7654321bit 0 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a reset:00000000 table 9-2 timer control configuration edgxb edgxa configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system 9-6 technical data 9.2.2 timer input capture registers when an edge has been detected and synchronized, the 16-bit free-running counter value is transferred into the input capture register pair as a single 16-bit parallel trans- fer. timer counter value captures and timer counter incrementing occur on opposite half-cycles of the phase two clock so that the count value is stable whenever a capture occurs. the ticx registers are not affected by reset. input capture values can be read from a pair of 8-bit read-only registers. a read of the high-order byte of an input capture register pair inhibits a new capture transfer for one bus cycle. if a double-byte read in- struction, such as ldd, is used to read the captured value, coherency is assured. when a new input capture occurs immediately after a high-order byte read, transfer is delayed for an additional cycle but the value is not lost. 9.2.3 timer input capture 4/output compare 5 register use ti4/o5 as either an input capture register or an output compare register, depend- ing on the function chosen for the i4/o5 pin. to enable it as an input capture pin, set the i4/o5 bit in the pulse accumulator control register (pactl) to logic level one. to use it as an output compare register, set the i4/o5 bit to a logic level zero. refer to 9.6 pulse accumulator . 9.3 output compare use the output compare (oc) function to program an action to occur at a specific time when the 16-bit counter reaches a specified value. for each of the five output com- pare functions, there is a separate 16-bit compare register and a dedicated 16-bit com- parator. the value in the compare register is compared to the value of the free-running counter on every bus cycle. when the compare register matches the counter value, an output compare status flag is set. the flag can be used to initiate the automatic actions for that output compare function. to produce a pulse of a specific duration, write to the output compare register a value representing the time the leading edge of the pulse is to occur. the output compare circuit is configured to set the appropriate output either high or low, depending on the tic1Ctic3 timer input capture $0010C$0015 $0010 bit 15 14 13 12 11 10 9 bit 8 tic1 (high) $0011bit 7654321bit 0tic1 (low) $0012 bit 15 14 13 12 11 10 9 bit 8 tic2 (high) $0013bit 7654321bit 0tic2 (low) $0014 bit 15 14 13 12 11 10 9 bit 8 tic3 (high) $0015bit 7654321bit 0tic3 (low) reset: input capture registers not affected by reset. ti4/o5 timer input capture 4/output compare 5 $001e, $001f $ 0 01e bit 15 14 13 12 11 10 9 bit 8 ti4/o5 (high) $ 0 01f bit 7 6 5 4 3 2 1 bit 0 ti4/o5 (low) reset: all i4/o5 register pairs reset to ones ($ffff). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system technical data 9-7 polarity of the pulse being produced. after a match occurs, the output compare register is reprogrammed to change the output pin back to its inactive level at the next match. a value representing the width of the pulse is added to the original value, and then writ- ten to the output compare register. because the pin state changes occur at specific values of the free-running counter, the pulse width can be controlled accurately at the resolution of the free-running counter, independent of software latencies. to generate an output signal of a specific frequency and duty cycle, repeat this pulse-generating procedure. there are four 16-bit read/write output compare registers: toc1, toc2, toc3, and toc4, and the ti4/o5 register, which functions under software control as either ic4 or oc5. each of the oc registers is set to $ffff on reset. a value written to an oc register is compared to the free-running counter value during each e-clock cycle. if a match is found, the particular output compare flag is set in timer interrupt flag register 1 (tflg1). if that particular interrupt is enabled in the timer interrupt mask register 1 (tmsk1), an interrupt is generated. in addition to an interrupt, a specified action can be initiated at one or more timer output pins. for oc5Coc2, the pin action is controlled by pairs of bits (omx and olx) in the tctl1 register. the output action is taken on each successful compare, regardless of whether or not the ocxf flag in the tflg1 register was previously cleared. oc1 is different from the other output compares in that a successful oc1 compare can affect any or all five of the oc pins. the oc1 output action taken when a match is found is controlled by two 8-bit registers with three bits unimplemented: the output compare 1 mask register, oc1m, and the output compare 1 data register, oc1d. oc1m specifies which port a outputs are to be used, and oc1d specifies what data is placed on these port pins. 9.3.1 timer output compare registers all output compare registers are 16-bit read-write. each is initialized to $ffff at reset. if an output compare register is not used for an output compare function, it can be used as a storage location. a write to the high-order byte of an output compare register pair inhibits the output compare function for one bus cycle. this inhibition prevents inap- propriate subsequent comparisons. coherency requires a complete 16-bit read or write. however, if coherency is not needed, byte accesses can be used. for output compare functions, write a comparison value to output compare registers toc1Ctoc4 and ti4/o5. when tcnt value matches the comparison value, speci- fied pin actions occur. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system 9-8 technical data all tocx register pairs reset to ones ($ffff) ti4/o5 timer input capture 4/output compare 5 $001e, $001f refer to 9.2.3 timer input capture 4/output compare 5 register . 9.3.2 timer compare force register the cforc register allows forced early compares. foc[1:5] correspond to the five output compares. these bits are set for each output compare that is to be forced. the action taken as a result of a forced compare is the same as if there were a match be- tween the ocx register and the free-running counter, except that the corresponding interrupt status flag bits are not set. the forced channels trigger their programmed pin actions to occur at the next timer count transition after the write to cforc. the cforc bits should not be used on an output compare function that is pro- grammed to toggle its output on a successful compare because a normal compare that occurs immediately before or after the force can result in an undesirable operation. foc1Cfoc5 write ones to force compare(s) 0 = not affected 1 = output x action occurs bits [2:0] not implemented, always read zero 9.3.3 output compare mask registers use oc1m with oc1 to specify the bits of port a that are affected by a successful oc1 compare. the bits of the oc1m register correspond to pa[7:3]. toc1Ctoc4 timer output compare $0016C$001d $0016 bit 15 14 13 12 11 10 9 bit 8 toc1 (high) $0017bit 7654321bit 0toc1 (low) $0018 bit 15 14 13 12 11 10 9 bit 8 toc2 (high) $0019bit 7654321bit 0toc2 (low) $001a bit 15 14 13 12 11 10 9 bit 8 toc3 (high) $001bbit 7654321bit 0toc3 (low) $001c bit 15 14 13 12 11 10 9 bit 8 toc4 (high) $001dbit 7654321bit 0toc4 (low) cforc timer compare force $000b bit 7654321bit 0 foc1 foc2 foc3 foc4 foc5 0 0 0 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system technical data 9-9 oc1m7Coc1m3 output compare masks 0 = oc1 is disabled 1 = oc1 is enabled to control the corresponding pin of port a bits [2:0] not implemented; always read zero set bit(s) to enable oc1 to control corresponding pin(s) of port a. 9.3.4 output compare 1 data register use this register with oc1 to specify the data that is to be stored on the affected pin of port a after a successful oc1 compare. when a successful oc1 compare occurs, a data bit in oc1d is stored in the corresponding bit of port a for each bit that is set in oc1m. if oc1mx is set, data in oc1dx is output to port a bit x on successful oc1 compares. bits [2:0] not implemented; always read zero 9.3.5 timer counter register the 16-bit read-only tcnt register contains the prescaled value of the 16-bit timer. a full counter read addresses the most significant byte (msb) first. a read of this address causes the least significant byte (lsb) to be latched into a buffer for the next cpu cy- cle so that a double-byte read returns the full 16-bit state of the counter at the time of the msb read cycle. tcnt resets to $0000. in normal modes, tcnt is read-only. 9.3.6 timer control 1 register the bits of this register specify the action taken as a result of a successful ocx com- pare. oc1m output compare 1 mask $000c bit 7654321bit 0 oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 reset:00000000 oc1d output compare 1 data $000d bit 7654321bit 0 oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 reset:00000000 tcnt timer counter $000e, $000f $ 0 00e bit 15 14 13 12 11 10 9 bit 8 tcnt (high) $ 0 00fbit 765432 1 bit 0 tcnt (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system 9-10 technical data om[2:5] output mode ol[2:5] output level these control bit pairs are encoded to specify the action taken after a successful ocx compare. oc5 functions only if the i4/o5 bit in the pactl register is clear. refer to the following table for the coding. 9.3.7 timer interrupt mask 1 register use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts. oc1iCoc4i output compare x interrupt enable if the ocxi enable bit is set when the ocxf flag bit is set, a hardware interrupt se- quence is requested. i4/o5i input capture 4 or output compare 5 interrupt enable when i4/o5 in pactl is one, i4/o5i is the input capture 4 interrupt enable bit. when i4/o5 in pactl is zero, i4/o5i is the output compare 5 interrupt enable bit. ic1iCic3i input capture x interrupt enable if the icxi enable bit is set when the icxf flag bit is set, a hardware interrupt sequence is requested. note bits in tmsk1 correspond bit for bit with flag bits in tflg1. ones in tmsk1 enable the corresponding interrupt sources. 9.3.8 timer interrupt flag 1 register bits in this register indicate when timer system events have occurred. coupled with the bits of tmsk1, the bits of tflg1 allow the timer subsystem to operate in either a tctl1 timer control 1 $0020 bit 7654321bit 0 om2 ol2 om3 ol3 om4 ol4 om5 ol5 reset:00000000 omx olx action taken on successful compare 0 0 timer disconnected from output pin logic 0 1 toggle ocx output line 1 0 clear ocx output line to 0 1 1 set ocx output line to 1 tmsk1 timer interrupt mask 1 $0022 bit 7654321bit 0 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system technical data 9-11 polled or interrupt driven system. each bit of tflg1 corresponds to a bit in tmsk1 in the same position. clear flags by writing a one to the corresponding bit position(s). oc1fCoc5f output compare x flag set each time the counter matches output compare x value i4/o5f input capture 4/output compare 5 flag set by ic4 or oc5, depending on the function enabled by i4/o5 bit in pactl ic1fCic3f input capture x flag set each time a selected active edge is detected on the icx input line 9.3.9 timer interrupt mask 2 register use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. the timer prescaler control bits are included in this register. toi timer overflow interrupt enable 0 = tof interrupts disabled 1 = interrupt requested when tof is set to one rtii real-time interrupt enable refer to 9.4 real-time interrupt . paovi pulse accumulator overflow interrupt enable refer to 9.6 pulse accumulator . paii pulse accumulator input edge interrupt enable refer to 9.6 pulse accumulator . note bits in tmsk2 correspond bit for bit with flag bits in tflg2. ones in tmsk2 enable the corresponding interrupt sources. tflg1 timer interrupt flag 1 $0023 bit 7654321bit 0 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f reset:00000000 tmsk2 timer interrupt mask 2 $0024 bit 7654321bit 0 toi rtii paovi paii 0 0 pr1 pr0 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system 9-12 technical data pr[1:0] timer prescaler select these bits are used to select the prescaler divide-by ratio. in normal modes, pr[1:0] can only be written once, and the write must be within 64 cycles after reset. refer to table 9-1 for specific timing values. 9.3.10 timer interrupt flag 2 register bits in this register indicate when certain timer system events have occurred. coupled with the four high-order bits of tmsk2, the bits of tflg2 allow the timer subsystem to operate in either a polled or interrupt driven system. each bit of tflg2 corresponds to a bit in tmsk2 in the same position. clear flags by writing a one to the corresponding bit position(s). tof timer overflow interrupt flag set when tcnt changes from $ffff to $0000 rtif real-time (periodic) interrupt flag refer to 9.4 real-time interrupt . paovf pulse accumulator overflow interrupt flag refer to 9.6 pulse accumulator . paif pulse accumulator input edge interrupt flag refer to 9.6 pulse accumulator . bits [3:0] not implemented always read zero 9.4 real-time interrupt the real-time interrupt feature, used to generate hardware interrupts at a fixed periodic rate, is controlled and configured by two bits (rtr1 and rtr0) in the pulse accumu- lator control (pactl) register. the rtii bit in the tmsk2 register enables the interrupt capability. the four different rates available are a product of the mcu oscillator fre- quency and the value of bits rtr[1:0]. refer to the following table, which shows the periodic real-time interrupt rates. pr[1:0] prescaler 0 0 1 0 1 4 1 0 8 1 1 16 tflg2 timer interrupt flag 2 $0025 bit 7654321bit 0 tof rtif paovf paif 0 0 0 0 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system technical data 9-13 the clock source for the rti function is a free-running clock that cannot be stopped or interrupted except by reset. this clock causes the time between successive rti time- outs to be a constant that is independent of the software latencies associated with flag clearing and service. for this reason, an rti period starts from the previous time-out, not from when rtif is cleared. every time-out causes the rtif bit in tflg2 to be set, and if rtii is set, an interrupt request is generated. after reset, one entire real-time interrupt period elapses before the rtif flag is set for the first time. refer to the tmsk2, tflg2, and pactl regis- ters. 9.4.1 timer interrupt mask 2 register this register contains the real-time interrupt enable bits. toi timer overflow interrupt enable refer to 9.3 output compare . rtii real-time interrupt enable 0 = rtif interrupts disabled 1 = interrupt requested when rtif is set to one paovi pulse accumulator overflow interrupt enable refer to 9.6 pulse accumulator . paii pulse accumulator input edge refer to 9.6 pulse accumulator . note bits in tmsk2 correspond bit for bit with flag bits in tflg2. ones in tmsk2 enable the corresponding interrupt sources. 9.4.1 timer interrupt flag 2 register bits of this register indicate the occurrence of timer system events. coupled with the four high-order bits of tmsk2, the bits of tflg2 allow the timer subsystem to operate in either a polled or interrupt driven system. each bit of tflg2 corresponds to a bit in tmsk2 in the same position. rtr[1:0] e = 1 mhz e = 2 mhz e = 3 mhz e = x mhz 0 0 0 1 1 0 1 1 2.731 ms 5.461 ms 10.923 ms 21.845 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms (e/2 13 ) (e/2 14 ) (e/2 15 ) (e/2 16 ) tmsk2 timer interrupt mask 2 $0024 bit 7654321bit 0 toi rtii paovi paii 0 0 pr1 pr0 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system 9-14 technical data clear flags by writing a one to the corresponding bit position(s). tof timer overflow interrupt flag set when tcnt changes from $ffff to $0000 rtif real-time interrupt flag the rtif status bit is automatically set to one at the end of every rti period. to clear rtif, write a byte to tflg2 with bit 6 set. paovf pulse accumulator overflow interrupt flag refer to 9.6 pulse accumulator . paif pulse accumulator input edge interrupt flag refer to 9.6 pulse accumulator . bits [3:0] not implemented always read zero 9.4.2 pulse accumulator control register bits rtr[1:0] of this register select the rate for the real-time interrupt system. bit ddra3 determines whether port a bit three is an input or an output when used for general-purpose i/o. the remaining bits control the pulse accumulator. ddra7 data direction control for port a bit 7 refer to 9.6 pulse accumulator . paen pulse accumulator system enable refer to 9.6 pulse accumulator . pamod pulse accumulator mode refer to 9.6 pulse accumulator . pedge pulse accumulator edge control refer to 9.6 pulse accumulator . ddra3 data direction register for port a bit 3 refer to section 6 parallel i/o . i4/o5 input capture 4/output compare 5 refer to 9.2 input capture . tflg2 timer interrupt flag 2 $0025 bit 7654321bit 0 tof rtif paovf paif 0 0 0 0 reset:00000000 pactl pulse accumulator control $0026 bit 7654321bit 0 ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system technical data 9-15 rtr[1:0] rti interrupt rate select these two bits determine the rate at which the rti system requests interrupts. the rti system is driven by an e divided by 2 13 rate clock that is compensated so it is in- dependent of the timer prescaler. these two control bits select an additional division factor. 9.5 computer operating properly watchdog function the clocking chain for the cop function, tapped off of the main timer divider chain, is only superficially related to the main timer system. the cr[1:0] bits in the option register and the nocop bit in the config register determine the status of the cop function. refer to section 5 resets and interrupts for a more detailed dis- cussion of the cop function. 9.6 pulse accumulator the MC68HC11d3 has an 8-bit counter that can be configured to operate either as a simple event counter, or for gated time accumulation, depending on the state of the pamod bit in the pactl register. refer to the pulse accumulator block diagram, fig- ure 9-3 . in the event counting mode, the 8-bit counter is clocked to increasing values by an ex- ternal pin. the maximum clocking rate for the external event counting mode is the e clock divided by two. in gated time accumulation mode, a free-running e-clock ? 64 signal drives the 8-bit counter, but only while the external pai pin is activated. refer to table 9-3 . the pulse accumulator counter can be read or written at any time. rtr[1:0] e = 1 mhz e = 2 mhz e = 3 mhz e = x mhz 0 0 0 1 1 0 1 1 2.731 ms 5.461 ms 10.923 ms 21.845 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms (e/2 13 ) (e/2 14 ) (e/2 15 ) (e/2 16 ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system 9-16 technical data figure 9-3 pulse accumulator pulse accumulator control bits are also located within two timer registers, tmsk2 and tflg2, as described in the following paragraphs. table 9-3 pulse accumulator timing common xtal frequencies selected crystal 4.0 mhz 8.0 mhz 12.0 mhz cpu clock (e) 1.0 mhz 2.0 mhz 3.0 mhz cycle time (1/e) 1000 ns 500 ns 333 ns pulse accumulator (in gated mode) (e/2 6 ) (e/2 14 ) 1 count - overflow - 64.0 s 16.384 ms 32.0 s 8.192 ms 21.33 s 5.461 ms pacnt 8-bit counter 2:1 mux pa7/ enable overflow 1 2 interrupt requests internal data bus input buffer & edge detection pactl tflg2 tmsk2 paovi paii ddra7 paen pamod pedge paovf paif 11 pulse acc block output buffer pai edge paen e 64 clock (from main timer) pai/oc1 from main timer oc1 disable flag setting f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system technical data 9-17 9.6.1 pulse accumulator control register four of this register's bits control an 8-bit pulse accumulator system. another bit en- ables either the oc5 function or the ic4 function, while two other bits select the rate for the real-time interrupt system. ddra7 data direction control for port a bit 7 the pulse accumulator uses port a bit 7 as the pai input, but the pin can also be used as general-purpose i/o or as an output compare. note that even when port a bit 7 is configured as an output, the pin still drives the input to the pulse accumulator. refer to section 6 parallel i/o for more information. paen pulse accumulator system enable 0 = pulse accumulator disabled 1 = pulse accumulator enabled pamod pulse accumulator mode 0 = event counter 1 = gated time accumulation pedge pulse accumulator edge control this bit has different meanings depending on the state of the pamod bit, as shown in the following table: ddra3 data direction register for port a bit 3 refer to section 6 parallel i/o . i4/o5 input capture 4/output compare 5 refer to 9.2 input capture . rtr[1:0] rti interrupt rate selects refer to 9.4 real-time interrupt . 9.6.2 pulse accumulator count register this 8-bit read/write register contains the count of external input events at the pai in- put, or the accumulated count. the counter is not affected by reset and can be read or written at any time. counting is synchronized to the internal ph2 clock so that incre- menting and reading occur during opposite half cycles. pactl pulse accumulator control $0026 bit 7654321bit 0 ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 reset:00000000 pamod pedge action on clock 0 0 pai falling edge increments the counter. 0 1 pai rising edge increments the counter. 1 0 a zero on pai inhibits counting. 1 1 a one on pai inhibits counting. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system 9-18 technical data 9.6.3 pulse accumulator status and interrupt bits the pulse accumulator control bits, paovi and paii, paovf, and paif are located within timer registers tmsk2 and tflg2. paovi and paovf pulse accumulator interrupt enable and overflow flag the paovf status bit is set each time the pulse accumulator count rolls over from $ff to $00. to clear this status bit, write a one in the corresponding data bit position (bit 5) of the tflg2 register. the paovi control bit allows configuring the pulse accumulator overflow for polled or interrupt-driven operation and does not affect the state of paovf. when paovi is zero, pulse accumulator overflow interrupts are inhibited, and the system operates in a polled mode, which requires paovf to be polled by user soft- ware to determine when an overflow has occurred. when the paovi control bit is set, a hardware interrupt request is generated each time paovf is set. before leaving the interrupt service routine, software must clear paovf by writing to the tflg2 register. paii and paif pulse accumulator input edge interrupt enable and flag the paif status bit is automatically set each time a selected edge is detected at the pa7/pai/oc1 pin. to clear this status bit, write to the tflg2 register with a one in the corresponding data bit position (bit 4). the paii control bit allows configuring the pulse accumulator input edge detect for polled or interrupt-driven operation but does not af- fect setting or clearing the paif bit. when paii is zero, pulse accumulator input inter- rupts are inhibited, and the system operates in a polled mode. in this mode, the paif bit must be polled by user software to determine when an edge has occurred. when the paii control bit is set, a hardware interrupt request is generated each time paif is set. before leaving the interrupt service routine, software must clear paif by writing to the tflg register. pacnt pulse accumulator count $0027 bit 7654321bit 0 bit 7654321bit 0 tmsk2 timer interrupt mask 2 $0024 bit 7654321bit 0 toi rtii paovi paii 0 0 pr1 pr0 reset:00000000 tflg2 timer interrupt flag 2 $0025 bit 7654321bit 0 tof rtif paovf paif 0 0 0 0 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics technical data a-1 appendix a electrical characteristics *one pin at a time, observing maximum power dissipation limits. internal circuitry protects the inputs against damage caused by high static voltages or electric fields; however, normal precautions are necessary to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. extended operation at the maximum ratings can adversely affect device reliability. tying unused inputs to an appropriate logic voltage level (either gnd or v dd ) enhances reliability of operation. notes: 1. this is an approximate value, neglecting p i/o . 2. for most applications p i/o ? p int and can be neglected. 3. k is a constant pertaining to the device. solve for k with a known t a and a measured p d (at equilibrium). use this value of k to solve for p d and t j iteratively for any value of t a . table a-1 maximum ratings rating symbol value unit supply voltage v dd C 0.3 to + 7.0 v input voltage v in C 0.3 to + 7.0 v operating temperature range mc6811d3 mc6811d3c mc6811d3v mc6811d3m t a t l to t h 0 to + 70 C 40 to + 85 C 40 to + 105 C 40 to + 125 c storage temperature range t stg C 55 to + 150 c current drain per pin* excluding v dd and v ss i d 25 ma table a-2 thermal characteristics characteristic symbol value unit average junction temperature t j t a + (p d x q ja ) c ambient temperature t a user-determined c package thermal resistance (junction-to-ambient) 44-pin plastic leaded chip carrier (plcc) 44-pin plastic quad flat pack (qfp) 52-pin plastic dip (p) q ja 50 50 50 c/w total power dissipation (note 1) p d p int + p i/o k / (tj + 273 c) w device internal power dissipation p int i dd x v dd w i/o pin power dissipation (note 2) p i/o user-determined w a constant (note 3) k p d x (t a + 273 c) + q ja x p d 2 w < c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics a-2 technical data notes: 1. v oh specification for reset and moda is not applicable because they are open-drain pins. v oh specification not applicable to ports c and d in wired-or mode. 2. extal is driven with a square wave, and t cyc = 1000 ns for 1 mhz rating; t cyc = 500 ns for 2 mhz rating; tcyc = 333 ns for 3 mhz rating; v il 0.2 v;v ih 3 v dd - 0.2 v; no dc loads. table a-3 dc electrical characteristics characteristic symbol min max unit output voltage (note 1) all outputs except xtal all outputs except xtal, reset , i load = 10.0 a and moda v ol v oh v dd C 0.1 0.1 v v output high voltage (note 1) all outputs except xtal, reset , and moda i load = C 0.8 ma, v dd = 4.5 v v oh v dd C 0.8 v output low voltage all outputs except xtal i load = 1.6 ma, v dd = 5.0 v v ol 0.4 v input high voltage all inputs except reset reset v ih 0.7 x v dd 0.8 x vdd v dd + 0.3 v dd + 0.3 v v input low voltage all inputs v il v ss C 0.3 0.2 x v dd v i/o ports, three-state leakage pa7, pa3, pb[7:0], pc[7:0], pd[7:0], v in = v ih or v il moda/lir , reset i oz 10 a input leakage current v in = v dd or v ss pa[2:0], irq , xirq v in = v dd or v ss modb/v stby i in 1 10 a a ram standby voltage power down v sb 4.0 v dd v ram standby current power down i sb 10 a input capacitance pa[2:0], irq , xirq , extal pa7, pa3, pb[7:0], pc[7:0], pd[7:0], moda/lir , reset c in 8 12 pf pf output load capacitance all outputs except pd[4:1] pd[4:1] c l 90 100 pf pf characteristic symbol 1 mhz 2 mhz unit maximum total supply current (note 2) run: single-chip mode v dd = 5.5 v expanded multiplexed mode v dd = 5.5 v wait: (all peripheral functions shut down) single-chip mode v dd = 5.5 v expanded multiplexed mode v dd = 5.5 v stop: single-chip mode, no clocks v dd = 5.5 v i dd w idd s idd 8 14 3 5 50 15 27 6 10 50 ma ma ma ma a maximum power dissipation single-chip mode v dd = 5.5 v expanded multiplexed mode v dd = 5.5 v p d 44 77 85 150 mw mw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics technical data a-3 figure a-1 test methods notes: 1. full test loads are applied during all dc electrical tests and ac timing measurements. 2. during ac timing measurements, inputs are driven to 0.4 volts and vdd C 0.8 volts while timing clocks, strobes inputs v dd C 0.8 volts 0.4 volts v dd ~ nominal timing nom. 20% of v dd 70% of v dd v dd C 0.8 volts 0.4 volts v ss ~ v dd ~ nom. outputs 0.4 volts dc testing clocks, strobes inputs 20% of v dd 70% of v dd v dd ~ spec timing v dd C 0.8 volts 20% of v dd 70% of v dd 0.4 volts v ss ~ v dd ~ spec outputs ac testing (note 2) 20% of v dd 70% of v dd 20% of v dd v ss ~ spec measurements are taken at the 20% and 70% of v dd points. test methods v ss ~ f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics a-4 technical data notes: 1. reset is recognized during the first clock cycle it is held low. internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. refer to section 5 resets and interrupts for further detail. 2. all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. figure a-2 timer inputs table a-4 control timing characteristic symbol 1.0 mhz 2.0 mhz 3.0 mhz unit min max min max min max frequency of operation f o dc 1.0 dc 2.0 dc 3.0 mhz e-clock period t cyc 1000 500 333 ns crystal frequency f xtal 4.08.012.0mhz external oscillator frequency 4 f o dc 4.0 dc 8.0 dc 12.0 mhz processor control setuptime t pcsu = 1/4 t cyc + 50 ns t pcsu 300 175 133 ns reset input pulse width to guarantee external reset vector minimum input time (can be preempted by internal reset) pw rstl 8 1 8 1 8 1 t cyc t cyc mode programming setup time t mps 222t cyc mode programming hold time t mph 10 10 10 ns interrupt pulse width, irq edge-sensitive mode pw irq = t cyc + 20 ns pw irq 1020 520 353 ns wait recovery startup time t wrs 444t cyc timer pulse width, input capture pulse accumulator input pw tim = t cyc + 20 ns pw tim 1020 520 353 ns notes: 1. rising edge sensitive input 2. falling edge sensitive input 3. maximum pulse accumulator clocking rate is e-clock frequency divided by 2. pa7 2,3 pa7 1,3 pa[2:0] 2 pa[2:0] 1 pw tim timer inputs tim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics technical data a-5 figure a-3 por and external reset timing diagram t pcsu address moda, modb e extal v dd reset 4064 t cyc fffe fffe fffe new pc fffe ffff fffe fffe fffe new pc fffe ffff fffe t mph pw rstl t mps por ext reset tim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics a-6 technical data figure a-4 stop recovery timing diagram pw irq t stopdelay 3 irq 1 irq or xirq e sp C 8 sp C 8 fff2 (fff4) new pc stop addr stop addr + 1 address 4 stop addr stop addr + 1 stop addr + 1 stop addr + 1 stop addr + 2 spspC7 fff3 (fff5) opcode resume program with instruction which f ollows the stop instruction. notes: 1. edge sensitive irq pin (irqe bit = 1) 2. level sensitive irq pin (irqe bit = 0) 3. t stopdelay = 4064 t cyc if dly bit = 1 or 4 t cyc if dly = 0. 4. xirq with x bit in ccr = 1. 5. irq or (xirq with x bit in ccr = 0). internal address 5 stop recovery tim clocks f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics technical data a-7 figure a-5 wait recovery timing diagram wait recovery tim t pcsu pcl pch, yl, yh, xl, xh, a, b, ccr stack registers e r/w address wait addr wait addr + 1 irq , xirq , or internal interrupts note: reset also causes recovery from wait. sp sp C 1 sp C 2sp C 8 sp C 8 sp C 8sp C 8 sp C 8 sp C 8 sp C 8 vector addr vector addr + 1 new pc t wrs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics a-8 technical data notes: 1. port c and d timing is valid for active drive (cwom and dwom bits not set in pioc and spcr registers respec- tively). 2. all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. figure a-6 port write timing diagram figure a-7 port read timing diagram table a-5 peripheral port timing characteristic symbol 1.0 mhz 2.0 mhz 3.0 mhz unit min max min max min max frequency of operation (e-clock frequency) f o dc 1.0 dc 2.0 dc 3.0 mhz e-clock period t cyc 1000 500 333 ns peripheral data setup time mcu read of ports a, b, c, and d t pdsu 100 100 100 ns peripheral data hold time mcu read of ports a, b, c, and d t pdh 50 50 50 ns delay time, peripheral data write mcu write to port a mcu writes to ports b, c, and d t pwd = 1/4 t cyc + 150 ns t pwd 200 350 200 225 200 183 ns ns d3 port write tim t pwd e mcu write to port previous port data previous port data new data valid new data valid ports b, c, d port a t pwd t pdh e mcu read of port t pdsu ports a, b, c, d d3 port read tim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics technical data a-9 notes: 1. input clocks with duty cycles other than 50% affect bus performance. timing parameters affected by input clock duty cycle are identified by (a) and (b). to recalculate the approximate bus timing values, substitute the following expressions in place of 1/8 t cyc in the above formulas, where applicable: (a) (1-dc) 1/4 t cyc (b) dc 1/4 t cyc where: dc is the decimal value of duty cycle percentage (high time). 2. all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. table a-6 expansion bus timing num characteristic symbol 1.0 mhz 2.0 mhz 3.0 mhz unit min max min max min max frequency of operation (e-clock frequency) f o dc 1.0 dc 2.0 dc 3.0 mhz 1 cycle time t cyc 1000 500 333 ns 2 pulse width, e low pw el = 1/2 t cyc - 23ns pw el 477 227 146 ns 3 pulse width, e high pw eh = 1/2 t cyc - 28 ns pw eh 472 222 141 ns 4a 4b e and as rise time e and as fall time t r t f 20 20 20 20 20 15 ns ns 9 address hold time t ah = 1/8 t cyc - 29.5 ns (note 1a) t ah 95.5 33 26 ns 12 non-muxed address valid time to e rise t av = pw el - (t asd + 80 ns) (note 1a) t av 281.5 94 54 ns 17 read data setup time t dsr 30 30 30 ns 18 read data hold time (max = t mad )t dhr 0 145.5 0 83 0 51 ns 19 write data delay time t ddw = 1/8 t cyc + 65.5 ns (note 1a) t ddw 190.5 128 71 ns 21 write data hold time t dhw = 1/8 t cyc - 30 ns (note 1a) t dhw 95.5 33 26 ns 22 muxed address valid time to e rise t avm = pw el - (t asd + 90 ns) (note 1a) t avm 271.5 84 54 ns 24 muxed address valid time to as fall t asl = pw ash - 70 ns t asl 151 26 13 ns 25 muxed address hold time t ahl = 1/8 t cyc - 30 ns (note 1b) t ahl 95.5 33 31 ns 26 delay time, e to as rise t asd = 1/8 t cyc - 5 ns (note 1a) t asd 115.5 53 31 ns 27 pulse width, as high pw ash = 1/4 t cyc - 30 ns pw ash 221 96 63 ns 28 delay time, as to e rise t ased = 1/8 t cyc - 5 ns (note 1b) t ased 115.5 53 31 ns 29 mpu address access time (note 1a) t acca = t cyc C (pw el C t avm ) C t dsr Ct f t acca 744.5 307 196 ns 35 mpu access time t acce = pw eh - t dsr t acce 442 192 111 ns 36 muxed address delay (previous cycle mpu read) t mad = t asd + 30 ns(note 1a) t mad 145.5 83 51 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics a-10 technical data figure a-8 multiplexed expansion bus timing diagram mux bus tim e as 1 4a 9 address/data (multiplexed) read write 12 2 3 4b 4a 4b 29 35 17 18 19 21 25 24 27 36 22 26 28 address address data data r/w , address (non-mux) note: measurement points shown are 20% and 70% of v dd . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics technical data a-11 notes: 1. all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. signal production depends on software. 3. assumes 100 pf load on all spi pins. table a-7 serial peripheral interface timing num characteristic symbol 2.0 mhz 3.0 mhz unit min max min max operating frequency master slave f op(m) f op(s) dc dc 0.5 2.0 dc dc 0.5 3.0 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 500 2.0 333 t cyc ns 2 enable lead time master (note 2) slave t lead(m) t lead(s) 250 240 ns ns 3 enable lag time master (note 2) slave t lag(m) t lag(s) 250 240 ns ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 340 190 340 190 ns ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 340 190 340 190 ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 100 100 100 100 ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 100 100 100 100 ns ns 8 access time (time to data active from high-imp. state) slave t a 0 120 0 120 ns 9 disable time (hold time to high-impedance state) slave t dis 240 167 ns 10 data valid (after enable edge) (note 3) t v(s) 240 167 ns 11 data hold time (outputs) (after enable edge) t ho 00 ns 12 rise time (20% v dd to 70% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t rm t rs 100 2.0 100 2.0 ns s 13 fall time (70% v dd to 20% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t fm t fs 100 2.0 100 2.0 ns s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics a-12 technical data figure a-9 spi master timing (cpha = 0) figure a-10 spi master timing (cpha = 1) spi master cpha0 tim see note note: this first clock edge is generated internally but is not seen at the sck pin. sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) ss (input) 1 see note 11 6 7 msb in bit 6 - - - -1 lsb in master msb out master lsb out bit 6 - - - -1 10 12 13 ss is held high on master. 5 4 13 12 11 (ref) 10 (ref) 13 4 5 12 spi master cpha1 tim note: this last clock edge is generated internally but is not seen at the sck pin. 4 5 5 4 1 see note 11 6 7 msb in lsb in master msb out master lsb out bit 6 - - - -1 10 13 12 13 12 sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) ss (input) ss is held high on master. see note 12 13 bit 6 - - - -1 11 (ref) 10 (ref) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics technical data a-13 figure a-11 spi slave timing (cpha = 0) figure a-12 spi slave timing (cpha = 1) spi slave cpha0 tim note: not defined but normally msb of character just received. 4 2 5 5 4 1 8 see note msb out slave slave lsb out 6 7 msb in 10 bit 6 - - - -1 lsb in 11 12 13 3 9 sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) ss (input) 11 12 13 bit 6 - - - -1 spi slave cpha1 tim note: not defined but normally lsb of character previously transmitted. 4 2 10 6 7 5 5 4 1 8 msb in see note msb out 10 slave bit 6 - - - -1 lsb in slave lsb out 11 13 12 12 13 3 9 sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) ss (input) bit 6 - - - -1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics a-14 technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical data and ordering information technical data b-1 appendix b mechanical data and ordering information b.1 pin assignments the MC68HC11d3 is available in the 40-pin dip, shown in figure b-1 , the 44-pin plcc, shown in figure b-2 , or the 44-pin quad flat pack (qfp), as shown in figure b-3 . refer to table b-1 for ordering information. figure b-1 40-pin dip pc7/addr7 xirq /v pp pd7/r/w pd6/as reset irq pd0/rxd pd1/txd pd2/miso pd3/mosi 9 10 11 12 13 14 15 16 17 18 pd4/sck 19 pd5/ss 20 pc6/addr6 8 pc5/addr5 7 pc4/addr4 6 pc3/addr3 5 pc2/addr2 4 pc1/addr1 3 pc0/addr0 2 v ss 1 pb5/addr13 pb6/addr14 pb7/addr15 pa0/ic3 pa1/ic2 pa2/ic1 pa3/ic4/oc5/oc1 pa5/oc3/oc1 pa7/pai/oc1 v dd 30 29 28 27 26 25 24 23 22 21 pb4/addr12 31 pb3/addr11 32 pb2/addr10 33 pb1/addr9 34 pb0/addr8 35 modb/v stby 36 moda/lir 37 e 38 extal 39 xtal 40 MC68HC(7)11d3 d3 40-pin dip f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC11d3 b-2 technical data figure b-2 44-pin plcc pc4/addr4 pc5/addr5 pc6/addr6 pc7/addr7 xirq/v pp pd7/r/ w pd6/as reset irq pd0/rxd pd1/txd pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 nc pa0/ic3 pa1/ic2 pc3/addr3 pc2/addr2 pc1/addr1 pc0/addr0 v ss ev ss xtal extal e moda/ lir modb/v stby pd2/miso pd3/mosi pd4/sck pd5/ ss v dd pa7/pa i /oc1 pa6/oc 2 /oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/ic4/oc5/oc1 pa2/ic1 7 8 9 10 11 12 13 14 15 16 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 17 pb1/addr9 38 pb0/addr8 39 MC68HC(7)11d3 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc... technical data b-3 figure b-3 44-pin qfp b.2 package dimensions for case outline information check our web site at http://www.motsps.com. b.3 ordering information add the proper suffix, from table b-1 , to the m68hc11- (or 711-) mcu number to specify the appropriate device when placing an order. figure b-4 identifies the codes used to identify specific mcu options. table b-1 ordering information mcu package temperature description suffix 40-pin dip C 40 to +85 c buffalo rom cp1 d3 44-pin plcc C 40 to +85 c buffalo rom cfn1 44-pin quad flat pack C 40 to +85 c buffalo rom cfbl 40-pin dip C 40 to +85 c no rom cp d0 44-pin plcc C 40 to +85 c no rom cfn 44-pin quad flat pack C 40 to +85 c no rom cfb pc4/addr4 pc5/addr5 pc6/addr6 pc7/addr7 xirq/v pp pd7/r/ w pd6/as reset irq pd0/rxd pd1/txd pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 nc pa0/ic3 pa1/ic2 pc3/addr3 pc2/addr2 pc1/addr1 pc0/addr0 v ss ev ss xtal extal e moda/ lir modb/v stby pd2/miso pd3/mosi pd4/sck pd5/ ss v dd pa7/pai/oc1 pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/ic4/oc5/oc1 pa2/ic1 2 3 4 5 6 7 8 9 10 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 43 42 41 40 39 38 37 36 35 34 pb1/addr9 32 pb0/addr8 MC68HC(7)11d3 1 44 33 22 11 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc... mechanical data and ordering information b-4 technical data figure b-4 m68hc11 part number options f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support technical data c-1 appendix c development support c.1 development system tools freescale has developed tools for use in debugging and evaluating m68hc11 equip- ment. refer to the following list for those development tools that are available for use with the MC68HC11d3. for information about freescale and third party development system hardware and software, contact your freescale sales representative. c.2 MC68HC11d3 development tools ? m68hc11d3evs evaluation system ? m68hc711d3pgmr programmer board ? m68hc711d3evb evaluation board f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support c-2 technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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